Interrupt Delay Controller Batching for Power Reduction
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Solution Overview
Problem
Portable devices experience high power consumption due to excessive processor thrashing caused by asynchronous and synchronous interrupts, leading to frequent active-to-inactive state transitions and reduced battery life.
Innovation Solution
Implementing a programmable interrupt delay controller that groups interrupts based on their criticality, allowing soft interrupts to be delayed and processed in batches, reducing the number of active-to-inactive state transitions and thus lowering power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the processor processes each interrupt immediately upon receipt, then interrupt response time is minimized, but power consumption increases due to frequent active-to-inactive state transitions
Solution Approach 1:
The interrupt delay controller pre-delays soft interrupts before they reach the processor core, batching them together so that multiple interrupts are handled in a single processor wake-up event. This preliminary action of delaying and batching interrupts reduces the frequency of active-to-inactive transitions while maintaining acceptable response times for non-critical interrupts.
Solution Approach 2:
The interrupt handling system is segmented into two paths: hard interrupts that require immediate processing and soft interrupts that can be delayed and batched. This segmentation allows the system to prioritize critical responses while reducing power consumption for non-critical events, resolving the contradiction between response time and power usage.
2Productivity
If the processor remains in active state to handle multiple interrupts, then interrupt processing efficiency improves, but power consumption increases
Solution Approach 1:
Multiple soft interrupts are merged into a single batch that is processed together during one processor active period. The interrupt delay controller accumulates multiple interrupt events and releases them simultaneously, allowing the processor to handle several interrupts in succession without returning to inactive state between each one, thus improving efficiency while controlling power consumption.
3Use of energy by moving object
If soft interrupts are delayed for batch processing, then power consumption is reduced, but interrupt response time increases
Solution Approach 1:
Different quality of service is applied to different interrupt types: hard interrupts receive immediate processing with zero delay, while soft interrupts are subjected to configurable delays for batching. This local differentiation in handling quality allows the system to reduce power consumption for non-critical interrupts without impacting the response time of critical hard interrupts.
Data Source
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AI summary
The present disclosure provides a processor comprising at least one core including a first core, an interrupt controller and interrupt delay logic to: receive a first interrupt at a first time; delay the first interrupt from being processed by a first time delay that begins at the first time unless the first interrupt is pending at a second time when a second interrupt is processed by the first core; and if the first interrupt is pending at the second time, indicate to the first core to begin to process the first interrupt prior to completion of the first time delay, wherein the second interrupt is received periodically. The interrupt delay logic is further to: receive a third interrupt at a third time and assign to the third interrupt a second time delay, delay processing of the third interrupt from the third time by the second time delay unless the third interrupt is pending while the first interrupt or the second interrupt are being processed; if the third interrupt is pending while the first interrupt or the second interrupt is being processed, indicate to the first core to process the third interrupt without completion of the second time delay; if the third interrupt is not pending while the first interrupt is to be processed, the interrupt delay logic is to indicate to the core to process the third interrupt after completion of the second time delay.