Non-linear Termination for On-Package I/O Interfaces
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Solution Overview
Problem
Conventional high-bandwidth interconnections between chips require significant power and chip area, making them undesirable for applications needing reduced power consumption and smaller chip sizes.
Innovation Solution
The development of on-package input/output (OPIO) interfaces that utilize single-ended, high-speed CMOS interfaces with impedance-matched transmitters, forwarded clock signals, and reduced electrostatic discharge protection to achieve high bandwidth with low power, area, and latency, along with a non-linear feedback inverter termination scheme to minimize power and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections between chips, then bandwidth is achieved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent changes the termination impedance parameter from conventional fixed values to voltage-dependent non-linear values. The termination impedance is set to approximately 50 ohms for differential signals and 25 ohms for single-ended signals, optimizing power efficiency while maintaining signal integrity at high bandwidths
Solution Approach 2:
The patent introduces dynamic termination impedance that varies with signal voltage levels. The non-linear termination provides different impedance values for different signal conditions, enabling adaptive power management that reduces power consumption during low-activity periods while maintaining high bandwidth capability during peak transmission
2Productivity
If conventional I/O interfaces are used for high-bandwidth interconnections between chips, then bandwidth is achieved, but chip area increases significantly
Solution Approach 1:
The patent optimizes the termination impedance parameter to reduce the number and size of passive components required. By using non-linear termination with specific impedance values (50 ohms differential, 25 ohms single-ended), the design achieves high bandwidth with minimized chip area footprint
Solution Approach 2:
The patent extracts and eliminates unnecessary termination components from conventional designs. The non-linear termination approach removes the need for multiple large passive resistors and complex termination networks, retaining only the essential elements needed for high-bandwidth operation
3Use of energy by moving object
If non-linear termination is implemented, then power and area are reduced, but signal integrity must be maintained
Solution Approach 1:
The patent carefully selects and adjusts the termination impedance parameters to simultaneously optimize power consumption and signal integrity. The non-linear termination impedance is tuned to provide optimal signal matching across different voltage levels, preventing reflections and maintaining signal quality
Solution Approach 2:
The patent implements feedback mechanisms that monitor signal quality and dynamically adjust termination parameters. This feedback control ensures that signal integrity is maintained even as power consumption is reduced through non-linear termination
Data Source
AI summary
An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.