QDMA Queue Traffic Management for FPGA Heterogeneous Accelerators
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Solution Overview
Problem
Current FPGA heterogeneous accelerators lack effective traffic management and control capabilities, leading to insufficient network traffic processing and management, which hampers performance.
Innovation Solution
A method and apparatus for traffic management and control that acquire data frames from heterogeneous accelerators, select appropriate traffic management modes, and allocate data to QDMA queues, using techniques like RSS hashing and bandwidth statistics to ensure efficient processing by corresponding CPU cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional DMA interface is used to map memory resource on FPGA accelerator to host CPU, then the system structure is simple, but the bandwidth for host to access onboard RAM is completely shared with all kernels and has no traffic management and control capability
Solution Approach 1:
The patent divides the shared memory bandwidth into multiple dedicated queues (QDMA queues), where each queue can be independently configured and managed. This segmentation allows different kernels to have dedicated bandwidth channels, eliminating the need for complex runtime arbitration while providing traffic management capabilities through queue-specific configuration parameters.
Solution Approach 2:
The patent pre-configures bandwidth allocation and queue parameters before runtime operation. By establishing traffic management rules and bandwidth limits in advance through programming, the system avoids complex runtime decision-making while maintaining adaptability through configurable parameters that can be set according to different application requirements.
2Productivity
If an improved shell uses QDMA interface with additional AXIS interface, then user data can be directly exchanged with CPU memory without caching via FPGA accelerator memory, but there is no management and control mechanism and bandwidth allocation mechanism for the queue
Solution Approach 1:
The patent introduces configurable parameters for each QDMA queue including bandwidth limits, priority levels, and threshold values. These parameters can be adjusted to match different traffic patterns and performance requirements, providing management and control capabilities without requiring complex runtime mechanisms. The bandwidth allocation is controlled through programmable parameters that define queue behavior.
3Device complexity
If multiple kernels share the same CPU core for processing, then the device complexity is reduced, but the processing capability becomes insufficient when bandwidth exceeds single CPU core processing capability
Solution Approach 1:
The patent segments the processing workload by associating different QDMA queues with different CPU cores. Each queue can be independently directed to specific CPU cores based on configuration, enabling parallel processing across multiple cores when bandwidth requirements exceed single-core capabilities, while maintaining simple many-to-one mapping when lower performance is sufficient.
Data Source
AI summary
The present disclosure provides a method and apparatus for traffic management and control method, device and readable storage medium. The method includes: acquiring a data frame sent from a heterogeneous accelerator; selecting a target traffic management and control mode corresponding to data in the data frame from a plurality of preset traffic management and control modes; and managing and controlling the data in the data frame according to the target traffic management and control mode, so as to allocate the data to a QDMA queue, and send the data by the QDMA queue, and process the data by a corresponding CPU core.