Parallel Processing System Memory Broadcasting Architecture
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Solution Overview
Problem
Current parallel processing systems face challenges in effectively managing data access among multiple processors, leading to traffic contention and reduced processing efficiency due to shared memory limitations.
Innovation Solution
A parallel processing system comprising a bus, multiple parallel processing processors, and shared memories connected via separate channels and a memory connection line, with a main processor controlling data broadcasting between shared memories to minimize contention and optimize data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple processors share a common memory system, then data access is simplified, but traffic contention increases and processing efficiency decreases
Solution Approach 1:
The patent divides the memory system into multiple independent shared memories (first shared memory, second shared memory, etc.), each connected to processors through separate channels. This segmentation eliminates traffic contention by providing dedicated memory resources for different processor groups, thereby maintaining processing efficiency while simplifying data access through localized memory allocation.
Solution Approach 2:
The patent introduces a memory connection line that directly interconnects shared memories, creating a new dimensional pathway for data transfer independent of the processor bus. This additional dimension allows memories to exchange data directly without contending for processor memory access, resolving the contradiction between access simplicity and processing efficiency.
2Speed
If data is broadcast between shared memories, then data access speed increases, but system complexity increases
Solution Approach 1:
The patent pre-establishes memory connection lines between shared memories during system configuration, so that data broadcasting pathways are ready in advance. This preliminary action enables fast data access through pre-configured direct connections while avoiding the complexity of dynamic routing logic, as the broadcast path is determined statically during system setup.
Solution Approach 2:
The patent introduces a memory controller as an intermediary that manages data broadcasting between shared memories. The controller simplifies the broadcasting operation by automatically handling data routing and synchronization, thereby achieving high-speed data access without requiring complex coordination logic between processors and memories.
Data Source
AI summary
Provided are a parallel processing system and an operation method thereof. The parallel processing system includes: a bus; a plurality of parallel processing processors; a plurality of shared memories connected to the bus via separate individual channels and connected to each other via a memory connection line; and a main processor configured to set a broadcasting state for the plurality of shared memories and control data stored in one shared memory among the plurality of shared memories to be broadcast to another shared memory via the memory connection line according to the broadcasting state.