User-Level Interrupt Delivery Mechanism for Low Latency
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Solution Overview
Problem
Current processing systems incur latency due to privilege level transitions when delivering interrupts from I/O devices to user-level applications, as these transitions involve system calls, kernel mode interactions, and callback handlers, exceeding the operational latency of I/O devices.
Innovation Solution
Implementing a user-level interrupt delivery mechanism that allows interrupts to be directly delivered to user-level applications without kernel-level transitions, using a user-level Advanced Programmable Interrupt Controller (APIC) and user-level interrupt handler address data structures, enabling the processor to manage and prioritize interrupts within the user-level context.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If interrupts are delivered through the traditional kernel-level path, then system stability and security are maintained, but latency increases due to privilege level transitions
Solution Approach 1:
The patent segments the interrupt delivery path into two separate paths: a traditional kernel-level path for system calls and a new user-level path for I/O interrupts. This segmentation allows interrupts to be delivered directly to user-level applications without transitioning to kernel mode, reducing latency while maintaining system stability through the preserved kernel path for other operations.
Solution Approach 2:
The patent introduces a user-level Advanced Programmable Interrupt Controller (APIC) as an intermediary component that receives interrupts from I/O devices and delivers them directly to user-level applications. This intermediary eliminates the need for privilege level transitions while maintaining proper interrupt handling, resolving the contradiction between low latency and system stability.
2Productivity
If privilege level transitions are used for interrupt delivery, then system security is maintained, but operational efficiency decreases
Solution Approach 1:
The patent implements a dynamic interrupt delivery mechanism that adapts the privilege level based on the interrupt source and target. User-level applications can receive interrupts directly at user privilege level for improved efficiency, while the system retains the capability to transition to kernel level when necessary for security-critical operations, thus balancing productivity and reliability.
Solution Approach 2:
The patent changes the privilege level parameter from a fixed kernel-mode requirement to a flexible attribute that can be user-level for I/O interrupts. This parameter change enables direct user-level interrupt handling for better performance while maintaining kernel-level access for security-critical functions, resolving the contradiction between operational efficiency and system security.
3Loss of time
If multiple privilege level transitions occur during I/O operations, then proper system control is maintained, but latency exceeds I/O device operational latency
Solution Approach 1:
The patent extracts the interrupt handling functionality from the kernel level and places it at the user level, removing the unnecessary privilege level transitions from the I/O interrupt path. This extraction reduces software latency to below I/O device operational latency while maintaining system control through the preserved kernel interface for non-I/O operations.
Solution Approach 2:
The patent performs preliminary setup by installing user-level interrupt handlers and configuring the user-level APIC before I/O operations begin. This preliminary action enables direct user-level interrupt delivery without subsequent privilege level transitions, reducing latency while maintaining system control through pre-established security boundaries.
Data Source
AI summary
Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.