Layered Boundary Interconnect for FPGA Signal Routing

Solution Overview

Problem

The architecture of programmable logic devices, such as FPGAs, poses challenges in efficiently communicating signals between periphery interfaces and programmable logic regions due to bandwidth limitations and congestion, especially in vertical interfaces, which can hinder the effective use of corner areas in integrated circuit layouts.

Innovation Solution

A layered boundary interconnect is implemented, comprising a native transmission network for efficient signal transmission between input/output blocks and hard block circuits, and a protocol routing network between hard block circuits and programmable logic regions, along with boundary logic interfaces to enhance vertical bandwidth, allowing for flexible placement of input/output blocks and reducing routing congestion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a conventional single-layer interconnect architecture is used, then the layout area is simpler to manage, but the bandwidth and signal transmission efficiency between periphery interfaces and programmable logic regions deteriorates due to congestion

Engineering Contradiction:

Improvesignal transmission efficiencyVSAvoidinterconnect architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The interconnect architecture is segmented into multiple functional layers: a first layer for vertical signal transmission between periphery interfaces and programmable logic regions, and a second layer for horizontal signal transmission within programmable logic regions. This segmentation allows each layer to be optimized for its specific function, improving overall signal transmission efficiency while managing complexity through functional separation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the interconnect architecture by implementing a first layer that operates in the vertical direction between periphery interfaces and programmable logic regions, complementing the traditional horizontal second layer. This dimensional expansion creates additional signal transmission pathways, reducing congestion and improving bandwidth without proportionally increasing layout complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If input/output blocks are placed in corner areas of the IC layout, then the area utilization is improved, but the signal transmission capability and bandwidth in vertical interfaces deteriorates

Engineering Contradiction:

Improvearea utilizationVSAvoidvertical interface bandwidth

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The interconnect architecture is segmented into multiple functional layers: a first layer for vertical signal transmission between periphery interfaces and programmable logic regions, and a second layer for horizontal signal transmission within programmable logic regions. This segmentation allows each layer to be optimized for its specific function, improving overall signal transmission efficiency while managing complexity through functional separation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the interconnect architecture by implementing a first layer that operates in the vertical direction between periphery interfaces and programmable logic regions, complementing the traditional horizontal second layer. This dimensional expansion creates additional signal transmission pathways, reducing congestion and improving bandwidth without proportionally increasing layout complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If more routing resources are allocated to increase bandwidth, then the signal transmission capability is improved, but the routing congestion and latency in existing architectures worsens

Engineering Contradiction:

ImprovebandwidthVSAvoidrouting latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The interconnect architecture is segmented into multiple functional layers: a first layer for vertical signal transmission between periphery interfaces and programmable logic regions, and a second layer for horizontal signal transmission within programmable logic regions. This segmentation allows each layer to be optimized for its specific function, improving overall signal transmission efficiency while managing complexity through functional separation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Boundary logic interfaces are introduced as intermediary elements that facilitate efficient signal transmission between the first layer (vertical interconnect) and the second layer (horizontal interconnect). These intermediaries optimize the handoff of signals between layers, reducing latency and preventing routing congestion at interface points.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10929331B1Layered boundary interconnect

Publication Date: 2021.02.23 XILINX INC

AI summary

Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.