Semiconductor Package Bridge Die Power Delivery
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving fine pitch interconnections and efficient power delivery due to the limitations of traditional substrate materials and routing methods, which result in increased resistance and inductance, leading to degraded power quality and variability across integrated circuits.
Innovation Solution
The implementation of a semiconductor package with embedded bridge dies that provide a more rigid substrate, allowing for finer interconnections and direct vertical pathways for power and ground connections through the bulk of the bridge die, reducing the need for circuitous routing and enhancing power delivery quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional substrate materials and routing methods are used, then device complexity is reduced, but power delivery quality deteriorates due to increased resistance and inductance
Solution Approach 1:
The patent transitions from planar routing on the substrate surface to three-dimensional routing through the substrate bulk. Through-substrate vias and embedded conductors create vertical and depth-based pathways, enabling direct power delivery routes that cut through the substrate rather than routing around on the surface, thereby reducing inductance and resistance while managing complexity.
Solution Approach 2:
The patent embeds conductors and power pathways within the substrate structure itself, nesting multiple routing layers and conductor types (through-substrate vias, embedded traces, surface mounts) within the single substrate component. This nesting allows complex power delivery networks to be contained within the substrate without increasing overall device footprint or external complexity.
2Manufacturing precision
If fine pitch interconnections are implemented, then manufacturing precision must increase, but traditional substrates cannot support the required precision
Solution Approach 1:
The patent divides the substrate into functional regions with different precision requirements. Through-substrate vias are positioned at critical high-precision locations for fine pitch interconnections, while other areas use standard routing. This segmentation allows high manufacturing precision to be applied only where necessary, reducing overall fabrication complexity while enabling fine pitch connections where needed.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the substrate. Areas requiring fine pitch interconnections receive enhanced structural support, tighter tolerance control, and specialized conductor configurations, while other regions use standard substrate properties. This local quality approach enables high precision manufacturing only in specific locations, balancing manufacturing ease with performance requirements.
3Loss of energy
If circuitous routing is used for power delivery, then device complexity is reduced, but power delivery efficiency deteriorates due to increased resistance and inductance
Solution Approach 1:
The patent creates three-dimensional power delivery pathways through the substrate bulk using through-substrate vias and embedded conductors. These vertical and depth-based routes provide direct shortcuts for power delivery, eliminating the need for long circuitous surface paths. The dimensional transition reduces both resistance and inductance by shortening current paths, while the integrated substrate structure manages the added routing complexity.
Data Source
AI summary
Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.