Bridge Fused Multiply-Adder Circuit for Efficient (A×B)+C Execution
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Solution Overview
Problem
Existing fused multiply-adder circuits in digital signal processing and graphics processing lack efficient integration of floating-point adder and multiplier operations, leading to suboptimal performance in executing (A×B)+C equations, which are crucial for digital signal processing and graphics processing.
Innovation Solution
A bridge fused multiply-adder circuit is introduced, comprising an alignment module, a carry-save adder tree, and an add/round module, allowing for parallel processing of floating-point addition and multiplication or serial processing of fused multiply-add instructions, reusing existing hardware to maintain low power and area costs while supporting both stand-alone and fused operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated fused multiply-adder circuit is implemented, then the execution efficiency of (A×B)+C operations is improved, but the hardware area and power consumption increase
Solution Approach 1:
The patent implements a fused multiply-adder circuit that can perform multiple operations including dedicated fused multiply-add (A×B)+C, standalone multiplication A×B, and standalone addition A+B by using multiplexers to route operands. This multi-functional design allows the circuit to achieve high execution efficiency for fused operations while sharing hardware resources to reduce area overhead compared to completely separate dedicated circuits for each operation type.
2Area of stationary object
If separate floating-point adder and multiplier circuits are used, then the hardware area is reduced, but the execution efficiency of fused multiply-add operations deteriorates
Solution Approach 1:
The patent merges the floating-point adder and multiplier circuits into a unified fused multiply-adder structure where the multiplication unit and addition unit share common hardware resources including the exponent alignment logic, significand addition circuitry, and rounding mechanism. This merging enables the circuit to perform fused multiply-add operations with single-instruction latency while maintaining a compact hardware footprint by eliminating redundant components that would exist in completely separate adder and multiplier circuits.
3Productivity
If existing hardware structures are modified to support fused operations, then the execution efficiency is improved, but the compatibility with existing floating-point operations may be compromised
Solution Approach 1:
The patent employs dynamic operand routing through multiplexers that can configure the circuit for different operation modes (fused multiply-add, standalone multiply, standalone add) based on the incoming instruction. The exponent alignment and significand processing paths are dynamically selected to match the required operation type, ensuring that the modified hardware structure maintains full compatibility with existing floating-point operations while enabling high-performance fused operations when needed.
Data Source
AI summary
A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardware “bridge” between an existing floating-point adder and a floating-point multiplier unit. This fused multiply-add functionality is added to existing two-operand architecture designs without degrading the performance or parallel pipe execution of floating-point adder and floating-point multiplier instructions.