A sensor system executes plug-in program modules in a closed microprocessor environment to adapt function scope dynamically.
Extends 5G FLUS control to support tunneling information between NBMP source and workflow manager.
A flow rule virtualization method merges multiple tenant rules into consolidated physical entries using a type table and rule map.
Information processing apparatus manages printer service permissions through automated contract status checks and administrator response handling.
A neural network processor segments layers into batches with temporary storage to update neuron states efficiently.
Model-based editing in a service registry ensures valid WS-Policy files by imposing constraints on user actions to prevent structural errors.
A compiler generates client APIs from server code to maintain communication interfaces.
An I/O client dynamically adjusts performance data resolution based on event rules to optimize system monitoring.
A radar processor allocates baseband processing resources to radio heads using specific RH-resource schemes.
Source and target applications control clipboard data transfer by registering custom formats and canceling operations via an intermediary API mechanism.
Modular tiles aggregate scattered control panels into a single canvas, eliminating tedious menu navigation.
Atomic compare and write memory instructions conditionally update data blocks using a lock word, reducing computational expense during concurrent access.
A storage controller migrates an execution context from a source computer to process input output tasks locally.
An auto-parallelizing compiler generates event-driven tuple-space programs using hierarchical mapping strategies.
Accelerated processing device enqueues tasks and generates user-level interrupts to activate a central processing unit thread.
Input data processing method aligns dimensions with operation units to enhance neural network controller performance.
A validation system detects network operation anomalies at software application boundaries to prevent error propagation.
Bridge fused multiply-adder circuit merges adder and multiplier hardware via dynamic routing, improving execution efficiency without increasing area.
Dividing signal and weight matrices into non-square fractional blocks enables flexible matrix multiplication operations.
Data-driven service templates automate telecommunication application provisioning without manual coding.
A feedback-directed compiling system inserts signatures in executable code to track execution frequency and identify hot sections for optimization.
A system extracts attributes and types from protocol buffer compiler generated Java classes to build structured data models automatically.
Virtual leaf driver nodes split leaf buffer outputs into equal-length paths to drive distributed clock grid points.
Virtual tape server initiates mainframe jobs using PSF and RSD commands over a FICON channel, bypassing conventional file transfer protocols.
A device placement system clusters machine learning operations using unsupervised graph analysis to optimize CPU-GPU distribution.
Encoding version identifiers in packets reduces load balancer processing and memory requirements while maintaining flow affinity across dynamic network changes.
Processor identifies common graphs across models to reuse computation instances, reducing redundant calculations and power consumption.
A workflow management system displays real-time completion status updates for affected stages via a graphical user interface.