Bridge Line Structure for 3D Memory Alignment Tolerance
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Solution Overview
Problem
In three-dimensional semiconductor devices, such as vertical NAND strings, misalignment between contact via structures and bit lines can cause electrical shorts or opens, leading to undesirable performance due to the high density and multilevel wiring requirements.
Innovation Solution
A monolithic three-dimensional memory device structure is developed, featuring a stack of alternating insulating and conductive layers with bridge line structures and contact via structures that connect bit lines and memory stack structures, ensuring precise electrical connections through the formation of bridge level via structures and dielectric material layers to prevent misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact via structures are formed to connect bit lines to memory stack structures in high density three-dimensional semiconductor devices, then electrical connection is achieved, but misalignment between contact via structures and bit lines causes electrical shorts or opens
Solution Approach 1:
The patent introduces bridge line structures as intermediary elements between the bit lines and contact via structures. These bridge lines are formed at a first level and extend in a first direction, providing additional alignment tolerance. The contact via structures are formed to contact these bridge lines rather than directly contacting bit lines, acting as a mediator that absorbs misalignment and ensures reliable electrical connection.
Solution Approach 2:
The patent employs multilevel wiring structures where bridge lines are formed at a first level and bit lines are formed at a second level (different vertical dimension). This dimensional separation allows the contact via structures to bridge between levels, providing alignment tolerance in the horizontal plane while maintaining vertical electrical connection. The bridge lines extend in a first direction while bit lines extend in a second direction, creating a two-dimensional alignment buffer.
2Quantity of substance
If multilevel metal interconnect structures are used to provide electrical wiring for high density circuitry, then wiring density increases, but the number of wiring levels increases leading to greater complexity
Solution Approach 1:
The patent segments the wiring function into multiple levels: bridge lines at a first level and bit lines at a second level. This segmentation allows each level to serve a specific function - bridge lines provide lateral connection and alignment tolerance, while bit lines provide vertical connection to memory stacks. By dividing the wiring task across levels, the structure achieves high wiring density without proportionally increasing overall complexity.
Solution Approach 2:
The bridge line structures serve multiple functions: they provide electrical connection between contact via structures, serve as alignment reference features for forming contact via holes, and enable lateral signal distribution. This multi-functionality reduces the need for separate dedicated structures, thereby increasing wiring density without linearly increasing the number of wiring levels.
Data Source
AI summary
A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.