Bridge-Linked Interposer Assembly for Mask-Limited Multi-Die Packaging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

As semiconductor integrated circuits shrink in size, connecting multiple functional dies through interposers becomes increasingly challenging, particularly in systems like chip-on-wafer-on-substrate (CoWoS), where issues such as stress and fabrication complexities arise from using single large interposers and stitching patterns exceed photolithographic mask limits.

Innovation Solution

The use of bridge components on a molded platform to partition and connect multiple chip-on-wafer structures, integrating multiple interposers to form a smaller, more reliable platform, reducing stress and avoiding stitching issues by using multiple smaller interposers and encapsulating with various materials and processes to ensure electrical connectivity and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single large interposer is used to connect multiple functional dies, then electrical connectivity between dies is achieved, but stress and fabrication complexities increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidfabrication complexities

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the interconnection system into multiple smaller interposers instead of using a single large interposer. Each interposer connects to a subset of functional dies, reducing the complexity and stress on individual interposers while maintaining overall electrical connectivity across all dies through the modular architecture.

Inventive Principle:

Principle #1Segmentation

2Reliability

If a single large interposer is used to connect multiple functional dies, then electrical connectivity between dies is achieved, but stress on the interposer increases

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstress on interposer

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Reliability

If stitching patterns are used to connect dies on a single interposer, then electrical connectivity is achieved, but stitching exceeds photolithographic mask limits

Engineering Contradiction:

Improveelectrical connectivityVSAvoidstitching precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

4Ease of manufacture

If multiple smaller interposers are used to reduce stress and complexity, then fabrication complexities are reduced, but device structure becomes more complex

Engineering Contradiction:

Improvefabrication easeVSAvoidstructure complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines multiple interposers and functional dies into an integrated assembly that is subsequently encapsulated as a single unit. The encapsulation process merges the separate components into a unified structure, simplifying the overall device architecture while maintaining the manufacturing advantages of using multiple smaller interposers.

Inventive Principle:

Principle #5Merging (Combining)

5Productivity

If multiple chip-on-wafer structures are integrated, then interconnection efficiency is improved, but stress management becomes more challenging

Engineering Contradiction:

Improveinterconnection efficiencyVSAvoidstress management

Core Design Contradiction:

ProductivityVSStress or pressure

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an encapsulation material that acts as an intermediary between the multiple chip-on-wafer structures. This encapsulation layer provides mechanical support and stress distribution, facilitating the integration of multiple structures while managing the stress challenges associated with high-density interconnections.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20240387385A1Semiconductor Devices and Methods of Manufacture

Publication Date: 2024.11.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.