Back-Side Illuminated Pixel Interconnect Layer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Back-side illuminated pixels in image sensors often suffer from low conversion gain and excess pixel readout noise, leading to poor performance.

Innovation Solution

The implementation of an interconnect layer that couples the floating diffusion region directly to the source follower transistor, with the reset transistor formed in the upper substrate layer to minimize effective capacitance and enhance conversion gain, while also acting as a reflector to increase photon conversion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If processing circuitry is formed underneath the photosensitive layer in back-side illuminated pixels, then incident light can reach the photosensitive layer without obstruction, but conversion gain decreases and readout noise increases

Engineering Contradiction:
Improvelight reach to photosensitive layerVSAvoidconversion gain and pixel performance
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent introduces an interconnect layer that extends vertically between upper and lower substrate layers, creating a three-dimensional connection path. This allows the floating diffusion region to be electrically connected to the source follower transistor through a vertical interconnect structure, resolving the spatial conflict between back-side illumination requirements and circuit functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The pixel structure is divided into upper and lower substrate layers with distinct functional regions. The upper substrate layer contains the photosensitive layer and floating diffusion region, while the lower substrate layer contains the source follower transistor. This segmentation allows each component to be optimized independently while maintaining electrical connectivity through the interconnect layer.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the floating diffusion region is directly connected to the source follower transistor through an interconnect layer, then conversion gain is enhanced, but device structure becomes more complex

Engineering Contradiction:
Improveconversion gainVSAvoidinterconnect layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interconnect layer serves multiple functions simultaneously: it provides electrical connection between the floating diffusion region and source follower transistor, acts as a reflector to enhance photon conversion in the photosensitive layer, and maintains the back-side illuminated architecture. This multi-functionality reduces the need for additional separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interconnect layer is formed from conductive material that combines electrical connectivity functionality with optical reflector properties. This composite structure eliminates the need for separate connection and reflection components, simplifying the overall device architecture while achieving both electrical and optical objectives.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in improved pixel performance with higher conversion gain and reduced readout noise, enhancing the overall efficiency of image sensors.

Implementation Method 1

the interconnect layer... acting as a reflector to increase photon conversion

Methodology Applied
Scientific EffectReflection: Reflection

Data Source

PatentEP4071820A1Back-side illuminated pixels with interconnect layers
Publication Date: 2022.10.12 SEMICON COMPONENTS IND LLC
  • EP4071820A1 patent drawingFigure 1
  • EP4071820A1 patent drawingFigure 2
  • EP4071820A1 patent drawingFigure 3

AI summary

A group of imaging pixels (100) comprises an upper substrate layer (30), a lower substrate layer (32), a floating diffusion region (52) in the upper substrate layer (30), for each pixel: a photodiode (PD1, PD2, PD3, PD4) in the upper substrate layer (30) that is coupled to the floating diffusion region (52), and for each pixel a transfer transistor (TX1, TX2, TX3, TX4) in the upper substrate layer (30), a source follower transistor (SF) in the lower substrate layer (32), and an interconnect layer (34) in between the upper substrate layer (30) and the lower substrate layer (32), wherein the interconnect layer (34) couples the floating diffusion region (52) directly to the source follower transistor (62).