Asymmetrical microlenses align optical axes with photodiodes to resolve non-uniform light distribution caused by varying incident angles.
A photosensitive capacitor pixel uses a coaxial conductive layer and dielectric to generate image signals via the photoelectric effect.
Lateral edge termination structures in silicon carbide avalanche photodiodes isolate the active detection region from peripheral charge generation.
Through-oxide vias link image sensor and digital signal processing dies via selective etching, reducing bond pad area and manufacturing complexity.
High-resistance substrates manage charge carrier depletion to reduce after pulsing and improve quantum yield in avalanche radiation detectors.
Multilayer band gap transition reduces current flow resistance and prevents Schottky layer peeling during wire bonding for reliable multi-wavelength detection.
Frontside and backside photodetector pairs reduce pixel-to-pixel color crosstalk caused by grid distortions during wafer thinning.
A TDI image sensor uses a segmented charge transport layer with separate gates to move electrical charges between photo-sensitive elements.
Pulsed light annealing crystallizes the buffer layer below 350°C, preventing thermal damage to the underlying CMOS substrate.
An energy conversion layer shifts blue photons to longer wavelengths, resolving spectral mismatch and boosting detection capability for high-energy light.
Vertical electrodes transfer charge through substrate zones, reducing crosstalk and image distortion in compact global shutter pixels.
A split-gate pixel architecture uses conditional reset and multi-bit sampling to convert photodetector signals efficiently.
Separating data and scan lines into distinct metal layers reduces line capacitance by 48%, improving TFT array yield and image quality.
A stacked image sensor uses a nested color filter array to direct mixed light spectra toward the photoelectric device.
Isolation structures suppress crosstalk and temperature-dependent signal variations in imaging devices.
Segmented pixel regions with insulating and metal barriers suppress secondary photon penetration, enhancing sensitivity while minimizing crosstalk noise.
Dividing the first electronic region into multiple segments increases charge accumulation capacity, allowing higher source-drain voltage without saturation.
Out-of-plane photodiode structures position sensor elements vertically above pixel circuitry to maximize optical fill factor in flat-panel imagers.
A photodetector apparatus uses a third layer to generate excitons that modulate the potential energy barrier of an electrical junction.
Recesses in the substrate layer conduct heat away from integrated circuits, reducing thermal noise while sliding electrical contacts ensure precise positioning.
Offset wirings and vias reduce parasitic capacity between vertical signal lines, lowering time constants for higher frame rates.
Selective area epitaxial growth and wafer bonding integrate III-V devices with silicon substrates, resolving lattice mismatch issues.
Collaborative pixels share optical area and redirect charge carriers to lower read noise while maintaining spatial resolution in ambient light.
A perimeter trench segments the handle bonding interface to stop delamination propagation while maintaining electrical connectivity through insulated vias.
Segmented pixel isolation sections suppress dark current increases while expanding saturated charge capacity in stacked solid-state image capture devices.
Interleaved pixel groups route signals to distinct connectors, reducing readout channel quantity and manufacturing cost.
A dual-layer photoconductor detector fills crystal pores with fine particles to enhance sensitivity and image resolution.
Radial n-type doping creates potential gradients that accelerate charge transfer to an edge-placed floating diffusion, resolving sensitivity-speed trade-offs.
Fusing adjacent nanocrystal cores creates an electrical network that boosts detectivity while eliminating complex assembly of separate epitaxial layers.
A receiver module integrates a self-conducting field-effect transistor to short-circuit voltage source contacts.
A photoelectric conversion apparatus uses recessed portions with insulation bodies to vary optical path lengths and reduce output ripple.
A dual-mode image sensor uses a signal-separating color filter array with multi-height spectral filters to route visible and infrared light.
Arranging dummy wiring lines in specific pixel regions equalizes density while minimizing light reflection from shorter wavelengths.
A conduction mesh with higher doping density reduces series resistance between adjacent diodes in a photo-detection device.
Segmenting pixels into sensitive and insensitive DEPFET subpixels suppresses signal distortion while maintaining precise exposure control.
Cadmium diffusion annealing creates spectral differentiation in CdHgTe pixels, eliminating trench etching defects that increase dark current.
Depletion portions between light-scattering particles prevent binder resin penetration, maintaining resolution while improving luminance.
Segmented bonding sheets isolate individual sensor chips, preventing positional shifts and maintaining imaging resolution in radiation detectors.
A wafer level image sensor packaging structure uses an encapsulant to reinforce the chip and prevent cracking during handling.
A pixel cell uses a PINNED structure with controlled doping to achieve nonlinear sensitivity.
A photo-sensitive device uses a segmented charge transport layer to control accumulated charges for read-out.
A semiconductor photon detector uses a rear bias layer and overlapping contact area to extend the depletion zone for efficient charge carrier separation.
Sliding edge constraints reduce internal stress during bending, enabling high curvature without fracture.
Segmenting the filter into buried and upper parts overcomes limited thickness constraints, boosting transmission for desired wavelengths.
Deep trench isolation with conductive fill extracts excess photoelectrons to prevent cross-talk between densely packed pixels.
A vertical interconnect layer connects the floating diffusion region to the source follower transistor, reducing effective capacitance and readout noise.
A 3D-integrated optical sensor uses a transparent spacer layer to define the working distance between an interference filter and an on-chip diffuser.
Interposing a silicon oxide stress relaxation layer between the microlens and resin suppresses surface wrinkling while maintaining optical focusing performance.
A backside illuminated sensor uses a doped layer to enhance quantum efficiency and light collection.
Preliminary underfill curing establishes mechanical strength before conductive vias form, preventing fragile bump bond failures.