GeSn SWIR Detector Integration on CMOS via Pulsed Annealing
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Solution Overview
Problem
Current methods for fabricating short-wave infrared (SWIR) detector arrays face challenges in achieving efficient integration with CMOS substrates at compatible temperatures, particularly due to lattice mismatch and dilatation coefficient differences between Si and GeSn materials, limiting the integration process and pixel size.
Innovation Solution
A method involving the deposition of a slightly doped buffer layer on a CMOS wafer, followed by light pulse annealing to crystallize the interface layer, allowing for the deposition of a GeSn absorption layer at temperatures below 350°C, enabling efficient charge collection and single-photon detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GeSn absorption layer is directly grown on Si CMOS substrate, then integration is simplified, but lattice mismatch and dilatation coefficient differences cause unreliable growth
Solution Approach 1:
A buffer layer is introduced as an intermediary between the Si CMOS substrate and the GeSn absorption layer. This buffer layer mediates the lattice mismatch and dilatation coefficient differences, enabling reliable growth of the GeSn layer while maintaining the simplified direct-growth integration approach.
Solution Approach 2:
The buffer layer allows for parameter changes in the growth process, specifically enabling the use of low growth temperatures (below 350°C) that are compatible with CMOS substrates. The buffer layer composition and structure can be optimized to gradually transition from Si to GeSn, reducing mismatch effects.
2Manufacturing precision
If high annealing temperatures are used to obtain buffer layer, then material quality improves, but CMOS substrate and conversion layer are damaged
Solution Approach 1:
Instead of continuous high-temperature annealing, the patent uses pulsed laser annealing with very short pulse durations. This periodic action delivers the necessary thermal energy to form the buffer layer while the short pulse duration prevents heat diffusion to the CMOS substrate, avoiding thermal damage.
Solution Approach 2:
The patent replaces conventional thermal annealing (a bulk heating process) with laser annealing (a localized, non-contact process). This substitution allows precise control of the annealing zone, heating only the buffer layer region without affecting the underlying CMOS substrate or overlying conversion layer.
3Adaptability or versatility
If bump bonding is used to integrate absorber, then any suitable semiconductor material can be used, but pixel size cannot be pushed below 50 μm
Solution Approach 1:
The patent merges the absorber layer and CMOS readout electronics into a single integrated structure through direct growth on the substrate, eliminating the need for separate bump bonding steps. This merging enables pixel sizes below 50 μm while maintaining material versatility through the buffer layer approach.
4Strength
If fusion bonding with patterned surface is used, then bonding strength improves, but structure complexity increases preventing widespread use
Solution Approach 1:
The patent extracts the complex bonding processes (bump bonding and fusion bonding) from the integration scheme entirely. By using direct epitaxial growth of the buffer layer and absorber on the CMOS substrate, the patent eliminates the need for separate bonding steps, patterned surfaces, and alignment procedures, dramatically simplifying the overall structure and manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a highly efficient, cost-effective, and scalable fabrication of SWIR detector arrays with reduced pixel size and power requirements, suitable for single-photon detection and energy-resolved imaging across the SWIR spectrum.
Implementation Method 1
C. sending light pulses, provided by a light source situated to the side of said slightly doped buffer layer opposite to said readout wafer, so as to crystallize said interface layer by the annealing effect of heat provided by the absorption of said light pulses by said interface layer
Implementation Method 2
crystallize said interface layer by the annealing effect of heat provided by the absorption of said light pulses by said interface layer
Data Source
Figure 1
Figure 2
Figure 3~5
AI summary
The invention relates to a low temperature method of fabrication of short-wave infrared (SWIR) detector focal plane arrays (FPA) comprising a readout wafer, comprising a p-n junction, and an absorption layer that are connected for improved performances. The absorber layer comprises a SWIR conversion layer that has a GeSn or a SiGeSn alloy composition. A slightly doped buffer layer consisting of Ge or GeSn is situated between the readout wafer and the absorber layer. The slightly doped buffer layer comprises a crystallized layer in contact with said readout wafer. The method of the invention is based on a first series of process steps to realize a CMOS processed readout wafer. A slightly doped buffer layer is then transferred on said readout wafer, the slightly doped buffer layer comprising an interface layer, in contact with said readout wafer, is crystallized, by annealing, at temperatures compatible with the CMOS processed readout wafer, by applying short light source pulses on said interface layer so as to achieve a high quality crystalline interface layer. The method is based on assuring a temperature profile between the light entrance surface of the slightly doped buffer layer and the readout electronics so that the annealing temperature remains compatible with the CMOS structure. The slightly doped buffer layer is then used for further grow, on top of it, a GeSn or SiGeSn layer to create a SWIR light conversion layer and achieve the final structure of the SWIR FPA. The invention also relates to a SWIR FPA detector as realized by the method of the invention. The invention also relates to a SWIR detection system 3 comprising the SWIR detector array 1 of the invention and an waveguide array comprising at least two waveguides, The invention relates further to SWIR FPA applications such as a multi/hyperspectral LIDAR imaging systems.