Synchronous Buck Converter Light-Load Mode Switching

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Solution Overview

Problem

Synchronous DC/DC converters face inefficiencies and slow response times when operating under light-load conditions, leading to compromised performance due to excessive switching and conduction losses.

Innovation Solution

Implementing a Light-load Efficiency (LLE) mode that alternates between burst and idle modes, using a controller with a voltage margin circuit and multiplexers to manage energy storage and release, and switching back to PWM mode when load increases, thereby reducing overall switching and conduction losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the synchronous buck converter operates in PWM mode under light-load conditions, then the response time to load changes is fast, but the switching and conduction losses increase significantly

Engineering Contradiction:
Improveswitching and conduction lossesVSAvoidresponse time to load changes
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

The system dynamically switches between PWM mode and light-load mode based on the actual load conditions. When the load is light, the controller activates light-load mode which uses burst cycling instead of continuous PWM switching, thereby reducing switching and conduction losses while maintaining adequate response capability for the given load conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The controller changes the operating parameters by transitioning from fixed-duty-cycle PWM switching to burst-mode operation with variable on-times. In light-load mode, the controller uses burst counting and threshold comparison to determine when to activate switching cycles, effectively changing the switching pattern to match the reduced load requirements and minimize energy losses

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If the synchronous buck converter shuts down under light-load conditions, then the energy efficiency increases, but the response time to return to full operation becomes unacceptable

Engineering Contradiction:
Improveenergy efficiencyVSAvoidresponse time to return to full operation
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

Instead of complete shutdown, the system employs periodic burst cycling where the converter operates in short bursts followed by idle periods. The burst counter increments during active periods and compares against a threshold to determine when to enter idle mode, creating a periodic operation pattern that maintains energy efficiency while ensuring rapid response capability when load increases

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The controller maintains readiness for full operation by using a burst counter and threshold comparison mechanism that allows quick transition from light-load mode back to PWM mode when needed. The preliminary setup of counter thresholds and comparison logic ensures that when load conditions change, the system can rapidly respond without prolonged delay

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8030909B2Method and apparatus for switching a synchronous DC/DC converter between a PWM mode of operation and a light-load mode of operation
Publication Date: 2011.10.04 TEXAS INSTRUMENTS INC
  • US8030909B2 patent drawing
  • US8030909B2 patent drawing
  • US8030909B2 patent drawing

AI summary

A synchronous buck converter operates in a PWM mode of operation and switches to light-load mode of operation under a light-load condition. When operating in the light-load mode, the synchronous buck converter transitions between a burst mode and an idle mode of operation. In the burst mode of operation, the converter operates with a fixed but increased duty ratio, with respect to the PWM mode of operation, that installs additional energy in an output capacitor. In the idle mode of operation, the high-side and low-side transistors are each turned off. To maximize energy savings and to quickly transition back to the PWM mode of operation if the load increases, a limit as to the number of allowed switching cycles when bursting is imposed and a minimum ratio of the number of clock cycles when idling to the number of switching cycles when bursting is set. Additionally, a comparator is provided to detect a sudden step-increase in the load to quickly switch the converter back to the PWM mode of operation.