Buffer Circuit Skew Reduction via Dynamic Current Mirrors
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Solution Overview
Problem
In high-speed signal transmission using DDR interfaces, misalignment of rise and fall times (skew) is a challenge, and providing multiple input buffer circuits to handle various I/O power supply voltages increases circuit area, which is inefficient.
Innovation Solution
A buffer circuit design incorporating current mirror circuits and transistors, activated by specific signals, allows for minimal skew across a range of input voltages without the need for multiple buffer circuits, using activating signals to control current mirror operations based on input voltage amplitudes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple input buffer circuits are provided to handle various I/O power supply voltages, then adaptability to different voltage conditions is improved, but circuit area increases
Solution Approach 1:
The patent implements a universal input buffer circuit that can handle multiple I/O power supply voltages (1.8V, 3.3V, 5V) through a single circuit design. The circuit uses voltage-dependent activation of current mirror circuits to adapt to different voltage conditions, eliminating the need for separate buffer circuits for each voltage level and thereby reducing circuit area while maintaining full voltage compatibility
Solution Approach 2:
The patent dynamically changes operational parameters based on input voltage amplitude. The activating signal generation circuit detects the input voltage level and adjusts the activation state of current mirror circuits accordingly. This parameter adaptation allows a single buffer circuit to function across multiple voltage conditions, resolving the contradiction between adaptability and circuit area
2Area of stationary object
If a single input buffer circuit is used to reduce circuit area, then circuit area is reduced, but maintaining small skew across various I/O power supply voltages becomes difficult
Solution Approach 1:
The patent employs dynamic activation of current mirror circuits based on real-time detection of input voltage amplitude. The activating signal generation circuit continuously monitors voltage levels and dynamically switches between different current mirror configurations (first current mirror for lower voltages, second current mirror for higher voltages). This dynamic adaptation ensures optimal skew performance across all voltage conditions while using a single static circuit structure
Solution Approach 2:
The patent implements a feedback mechanism where the activating signal generation circuit monitors the input voltage amplitude and provides feedback control to the current mirror circuits. Based on the detected voltage level, the feedback system adjusts which current mirror circuit is activated, ensuring that the buffer circuit maintains small skew regardless of the I/O power supply voltage being used
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces skew and minimizes circuit area by dynamically adjusting the input voltage settings for optimal signal alignment across a broad range of input voltages, effectively addressing the inefficiencies of multiple buffer circuits.
Implementation Method 1
a first current mirror circuit which passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal
Implementation Method 2
a second current mirror circuit which is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal
Data Source
AI summary
A buffer circuit includes a first current mirror circuit, a second current mirror circuit, a first transistor, and a second transistor. The first current mirror circuit passes a first mirror current through a second node, corresponding to a first current passed through a first node, and is activated based on a first activating signal. The second current mirror circuit is connected to the first node and the second node, passes a second mirror current through the second node, corresponding to a second current passed through the first node, and is activated based on a second activating signal. The first transistor has a gate to which a reference voltage is applied and has a drain connected to the first node. The second transistor has a gate to which an input voltage is applied and has a drain connected to the second node.