Threshold Modification In Field Effect Transistors TRIZ Cases
- Dynamic I/O Bias Circuit for Multi-Voltage Transistor Stress Control
Dynamic bias generation tracks voltage-domain changes to limit I/O transistor stress, leakage, and timing issues across 1.8V to 3.3V operation.
- Differential Oscillator Trimming with Back-Gate Comparator Tuning
Back-gate comparator tuning trims differential oscillator frequency with lower noise, low power use, and glitch-free on-the-fly adjustment.
- PMOS Interface Circuit for Power Backflow Blocking
A bias-controlled PMOS interface circuit blocks backflow into powered-off devices, cutting standby power loss and preserving proper power-off behavior.
- Synchronized Ring Oscillator Chopping for 1/f Noise Reduction
Stopping differential ring oscillators in a predefined state enables synchronized chopping, reducing 1/f noise without added power.
- Flash Threshold Logic Gates With Programmable Floating-Gate Weights
Floating-gate threshold logic enables fine-grained programmable weights, improving CMOS logic area, power, and speed while staying design-compatible.
- Output Buffer Circuit With Intermediate-Node Leakage Blocking
Intermediate-node voltage control blocks high-impedance leakage in thin- or medium-oxide output buffers without thick-oxide process cost.
- Body-Biased Multi-Level Transmitter for Low-Power Memory Links
Body bias control lets one transmitter generate multi-level memory signals without termination resistors, cutting DC current and circuit complexity.
- Logic Circuit Inversion Path for NBTI Aging Mitigation
Extra logic inversions balance p-channel MOSFET aging to stabilize pulse width and duty cycle in always-on, low-activity logic circuits.
- I/O Circuit Gate Tracking for High-Voltage Logic Protection
A gate-tracking and bias scheme lets an I/O circuit handle higher input voltages while preventing current leakage and protecting logic units.
- CMOS Receiver Threshold Tuning for Voltage and Temperature Stability
Parallel CMOS inverters with different threshold voltages stabilize digital receivers against supply and temperature variation.
- Input Buffer Replica Circuit for Stable Logic Threshold Sensing
A replica buffer and comparator adjust logic threshold voltage to keep input sensing accurate across process, temperature, and clock changes.
- CMOS Inverter Calibration for Differential-Mode Negative Resistance
Differential-mode calibration tunes cross-coupled CMOS inverters to match resistor resistance, improving op-amp accuracy.
- Driver Circuit Slew Rate Modulation for SDR and DDR Memory
Individually delayed timing signals stagger driver switching to stabilize node slew rates and preserve fast SDR and DDR memory access.
- Dynamic Input Sampling Circuit With Adjustable Setup-Hold Timing
Feedback-controlled inverter thresholds adjust setup and hold timing at clock edges to prevent mis-sampling of asynchronous digital inputs.
- Forward Bulk-Biasing Circuit for Transistor Leakage Reduction
A forward bulk-biasing circuit selectively biases transistor bulk terminals during state transitions to modulate threshold voltage.
- Input Buffer Circuit With Asymmetric Thresholds For Voltage Domain Adaptation
Asymmetric threshold circuits in an input buffer adapt voltage levels across power domains, preventing overload damage to receiving circuits.
- Switching Current Source Circuit for Fast Settling
A switching current source circuit uses mirror transistors and a voltage generating unit to control bias currents.