Driver Circuit Slew Rate Modulation for SDR and DDR Memory
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Solution Overview
Problem
Non-volatile semiconductor memories face challenges with inconsistent slew rates in data transmission due to skewed control signals, which limits data access time and requires frequency reduction, especially when switching between asynchronous single data rate (SDR) and synchronous double data rate (DDR) modes.
Innovation Solution
The implementation of a driver circuit with individually delayed timing signals from a timing circuit to control the arrival times of data signals at multiple driver circuits, allowing for modulation of the slew rate at the data node, and the option to disable the timing circuit when SDR mode does not require slew rate modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If slew rate modulation is implemented using individually delayed timing signals, then data access time is reduced and consistency is improved, but device complexity increases due to additional timing circuitry
Solution Approach 1:
The timing circuit is segmented into multiple independent delay elements (first delay element, second delay element, third delay element) that can be individually controlled. Each delay element receives the same clock signal but produces differently delayed timing signals, allowing granular control over when each driver circuit is activated. This segmentation enables precise slew rate modulation while keeping each individual delay element relatively simple in structure.
Solution Approach 2:
The timing circuit performs preliminary action by pre-delays the clock signal through multiple delay elements before distributing timing signals to driver circuits. This preliminary timing adjustment ensures that drivers are activated in the optimal sequence to achieve consistent slew rates, preventing the need for complex real-time adjustments during data transmission.
2Reliability
If frequency is reduced to compensate for inconsistent slew rates, then data transmission reliability is maintained, but productivity decreases
Solution Approach 1:
The system implements feedback by monitoring the slew rate consistency and adjusting the timing delays accordingly. The timing circuit receives feedback about transmission conditions and modifies the delay amounts in real-time to maintain optimal slew rates, allowing the system to operate at higher frequencies without sacrificing reliability.
Solution Approach 2:
The invention changes the timing parameters (delay amounts) of the control signals dynamically. By adjusting the delay values in the delay elements based on operating conditions, the system can maintain consistent slew rates across different frequencies and modes, enabling higher productivity without compromising reliability.
3Speed
If multiple driver circuits are activated simultaneously, then data transmission speed is maximized, but slew rate consistency deteriorates due to skewed control signals
Solution Approach 1:
The system introduces asymmetric timing delays to what would otherwise be symmetric simultaneous activations. Each driver circuit receives a timing signal with a specific asymmetric delay relative to the others, compensating for inherent skew in the control signals. This asymmetric approach balances the overall activation timing, achieving both high speed and consistency.
Solution Approach 2:
The timing circuit performs preliminary action by pre-delays the clock signal through multiple delay elements before distributing timing signals to driver circuits. This preliminary timing adjustment ensures that drivers are activated in the optimal sequence to achieve consistent slew rates, preventing the need for complex real-time adjustments during data transmission.
Data Source
AI summary
Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.