CMOS Receiver Threshold Tuning for Voltage and Temperature Stability
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Solution Overview
Problem
Conventional CMOS-based inverter circuits in digital data communication systems are vulnerable to temperature and voltage supply fluctuations, leading to inconsistent operation and requiring continuous trimming for functionality.
Innovation Solution
A circuit design incorporating multiple CMOS transistors with different threshold voltages connected in parallel, allowing for independent programming of switching threshold voltage and transconductance parameters, ensuring temperature independence and voltage supply stability through a decoding circuit that generates enable signals to balance transconductance parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional CMOS-based inverter circuit is used, then the circuit is easy to port across components and nodes with no static power consumption when disabled, but the operation is dependent on temperature and voltage supply variations
Solution Approach 1:
The patent applies parameter changes by using multiple CMOS transistors with different threshold voltages (VT) in parallel configurations. Specifically, it employs transistors with VT values of 0.7V, 0.9V, 1.1V, and 1.3V to create inverter circuits whose switching characteristics can be adjusted. This allows the receiver circuit to maintain consistent operation across temperature and voltage variations by selecting or combining transistors with appropriate threshold voltages, thereby resolving the reliability issue while preserving portability.
2Reliability
If multiple CMOS transistors with different threshold voltages are used in parallel, then temperature independence and voltage supply stability are achieved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the receiver circuit into multiple independent inverter circuits, each using CMOS transistors with specific threshold voltages. These segmented inverter circuits can be independently configured or selected based on operating conditions. The decoding circuit further segments the control by generating specific enable signals (e.g., EN0-EN3) that activate particular transistor combinations, thereby managing complexity through modular organization while achieving temperature independence and voltage stability.
Solution Approach 2:
The patent applies universality by designing a multi-functional receiver circuit where the same physical infrastructure (multiple CMOS transistors with different VT values) serves multiple purposes: temperature compensation, voltage supply stabilization, and programmable switching threshold adjustment. The decoding circuit enables a single set of transistors to function in different configurations, reducing overall device complexity while maintaining reliability across varying conditions.
Data Source
AI summary
Embodiments relate to a circuitry for digital data communication. The circuitry includes an inverter circuit connected between an input node and an output node. The inverter circuit has core circuits each of which includes a complementary metal-oxide-semiconductor (CMOS) transistor of a first type and a CMOS transistor of a second type having a first common gate node connected to the input node and a first common drain node connected to the output node. The circuitry further includes another inverter circuit of a switching threshold voltage different than that of the inverter circuit and connected between the input node and the output node. The other inverter circuit has core circuits each of which includes a CMOS transistor of a third type and a CMOS transistor of a fourth type having a second common gate node connected to the input node and a second common drain node connected to the output node.