Logic Circuit Inversion Path for NBTI Aging Mitigation
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Solution Overview
Problem
Negative bias temperature instability (NBTI) causes performance degradation in p-channel MOSFETs within logic circuits, leading to changes in pulse width and duty cycle of logic signals, especially when inactive for extended periods, making existing solutions like power gating and periodic toggling unsuitable for always-on applications with low signal activity.
Innovation Solution
Incorporating extra logic inversions into the signal path using XOR gate circuits and multiplexer circuits to mitigate NBTI effects by balancing the exposure of p-channel MOSFETs to aging, thereby maintaining the logic state and stability of output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power gating is used to power off inactive logic circuits, then NBTI aging is reduced, but handshaking complexity increases and power on/off time becomes too long for low signal activity applications
Solution Approach 1:
The patent extracts the problematic NBTI aging effect from the always-on logic circuit by selectively powering off specific circuits during low signal activity periods, while maintaining the overall system operational through controlled power gating of subsets of circuits
Solution Approach 2:
The patent implements dynamic power gating control where the power state of logic circuits is adjusted based on signal activity detection, transitioning between active and powered-off states to balance aging reduction with operational requirements
2Reliability
If periodic toggling is used to prevent NBTI aging, then aging is reduced, but logic state stability is disturbed and downstream circuits are impacted
Solution Approach 1:
The patent applies periodic power gating cycles to subsets of logic circuits, alternating which circuits remain active and which are powered off, ensuring all circuits receive periodic rest without continuous signal toggling that would disturb logic states
Solution Approach 2:
The patent segments the logic circuit into multiple subsets, applying power gating to different segments at different times, which prevents logic state disturbance in any single segment while still providing aging relief to all circuits over time
3Speed
If logic circuits remain always on to maintain low signal activity operation, then signal responsiveness is maintained, but NBTI aging causes pulse width and duty cycle variations
Solution Approach 1:
The patent changes the operational parameters of logic circuits by dynamically adjusting power states based on signal activity levels, allowing circuits to operate fully active during high activity (maintaining speed) and powered off during low activity (preventing aging and parameter drift)
Data Source
AI summary
Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.