Output Buffer Circuit With Intermediate-Node Leakage Blocking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor chips with thin or medium gate oxides experience higher leakage currents, which are not effectively managed in high-voltage applications, leading to increased manufacturing costs and process difficulties.

Innovation Solution

An output driver circuit using transistors with thin or medium gate oxides, equipped with a leakage prevention circuit that controls intermediate node voltages based on signal levels to block leakage currents, eliminating the need for thick gate oxide transistors and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If transistors with thin or medium gate oxide are used, then manufacturing cost and process complexity are reduced, but leakage current increases

Engineering Contradiction:
Improvemanufacturing cost and process complexityVSAvoidleakage current
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a leakage prevention circuit as an intermediary component between the thin/medium gate oxide transistors and the output pad. This circuit includes additional transistors and control logic that actively manage and block leakage current paths, allowing the use of thinner gate oxides without suffering from their inherent high leakage characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent dynamically changes the operational parameters of the transistor circuit by implementing a high-impedance state control mechanism. By adjusting the voltage levels and switching states of the transistors based on the enable signal and data input, the circuit modifies its electrical characteristics to minimize leakage current while maintaining thin gate oxide advantages.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If thick gate oxide transistors are used for high-voltage operation, then leakage current is minimized, but manufacturing cost and process complexity increase

Engineering Contradiction:
Improveleakage currentVSAvoidmanufacturing cost and process complexity
Core Design Contradiction:
Object-generated harmful factorsVSEase of manufacture

Solution Approach 1:

The patent segments the transistor circuit into multiple functional blocks with different gate oxide thicknesses optimized for their specific functions. The leakage prevention circuit uses thick gate oxide transistors for leakage blocking functions, while the main output driver uses thin/medium gate oxide transistors for high-speed switching, thereby combining the advantages of both approaches without requiring all transistors to be thick gate oxide.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different gate oxide thicknesses to different parts of the circuit based on their specific functional requirements. Thick gate oxide is used locally in the leakage prevention circuit where low leakage is critical, while thin/medium gate oxide is used in the main output driver where high-speed performance is prioritized, optimizing overall circuit performance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250233590A1Output driver and output buffer circuit including the same
Publication Date: 2025.07.17 SAMSUNG ELECTRONICS CO LTD
  • US20250233590A1 patent drawing
  • US20250233590A1 patent drawing
  • US20250233590A1 patent drawing

AI summary

An output driver includes a driving circuit electrically connected to a pad and including at least two transistors connected to each other in series, and a leakage prevention circuit configured to block a leakage current of the driving circuit. Gates of the at least two transistors are electrically connected to each other, and the leakage prevention circuit is configured to control a voltage level of an intermediate node between the at least two transistors based on a signal level of the pad.