Dynamic Input Sampling Circuit With Adjustable Setup-Hold Timing
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Solution Overview
Problem
Data sampling circuits face challenges in maintaining optimal setup and hold times due to asynchronous data signals and fixed inverter buffer delays, leading to potential data mis-sampling.
Innovation Solution
A digital sampling circuit with dynamically adjustable inverter buffer switching thresholds, where sampled data is fed back to control the switching thresholds of inverter buffers, allowing for dynamic adjustment of setup and hold times based on rising and falling edges of the system clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed inverter buffer delays are used, then circuit simplicity is maintained, but setup and hold timing cannot be dynamically adjusted leading to data mis-sampling
Solution Approach 1:
The patent applies dynamics by making the inverter buffer switching thresholds adjustable rather than fixed. Control signals dynamically modify the switching thresholds of the inverter buffers in the data path, enabling the setup and hold times to be adjusted in response to varying data arrival times, thus resolving the contradiction between timing adaptability and circuit complexity
Solution Approach 2:
The patent changes the switching threshold parameter of the inverter buffers to achieve dynamic timing adjustment. By modifying the switching threshold voltage of the inverter buffers based on data arrival time, the effective delay through the data path is adjusted, allowing the circuit to adapt timing without fundamentally changing the circuit architecture
2Reliability
If inverter buffers are used to process data signal, then signal buffering is achieved, but fixed delays cause timing violations when data is asynchronous with clock
Solution Approach 1:
The patent implements feedback by monitoring the arrival time of data edges relative to clock edges and using this information to adjust the switching thresholds of inverter buffers. The feedback mechanism ensures that the data path delay is dynamically optimized to meet setup and hold requirements, improving sampling accuracy while compensating for timing losses due to asynchronous data arrival
Data Source
AI summary
A new method to sample a digital input signal is achieved. The method comprises sampling a digital input processed through a first digital buffer. The sampling is at the rising edge of a system clock. The switching threshold of a second digital buffer is updated. The digital input processed through the second digital buffer is sampled. The sampling is at the falling edge of the system clock. The switching threshold of the first digital buffer is updated. A digital sampling circuit is achieved.