I/O Circuit Gate Tracking for High-Voltage Logic Protection

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Solution Overview

Problem

Input/output circuits in electronic devices face challenges in protecting logic units from voltage greater than their operating voltage, leading to potential current leakage and damage.

Innovation Solution

An input/output circuit design that includes a logic unit, a driver with PMOS and NMOS transistors, a gate-tracking circuit, and a bias unit to manage voltage levels, ensuring that the circuit can receive signals up to breakdown voltage without causing current leakage and protecting the logic unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the input/output circuit receives high voltage signals above the logic unit's operating voltage, then the circuit can interface with external circuits operating at different voltage levels, but current leakage and damage to the logic unit may occur

Engineering Contradiction:
Improvevoltage level compatibilityVSAvoidlogic unit protection
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a dedicated protection circuit positioned between the input/output terminal and the logic unit. This intermediary circuit receives high voltage signals from external circuits and conditions them before passing to the logic unit, preventing direct exposure to damaging voltage levels while maintaining voltage level compatibility across different interfaces

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protection circuit performs preliminary voltage conditioning and clamping before signals reach the logic unit. By pre-processing incoming high voltage signals and limiting voltage excursions in advance, the circuit prevents potential damage before it can affect the logic unit, ensuring reliability during high voltage interfacing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If protection circuits are added to prevent current leakage, then logic unit safety improves, but circuit complexity increases

Engineering Contradiction:
Improvelogic unit protectionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protection circuit applies protection measures locally at the input/output terminal where high voltage signals enter, rather than protecting the entire logic unit uniformly. This localized approach concentrates protection resources where they are most needed, preventing current leakage at the vulnerable interface point without unnecessarily complicating the rest of the logic unit circuitry

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the input/output circuit into distinct functional blocks: the protection circuit handling high voltage interfacing and the logic unit handling logical operations. This segmentation isolates the complexity of voltage protection in a separate module, allowing the logic unit to remain simple while still achieving comprehensive protection through the dedicated protection circuit

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10985754B1Input/output circuit and electronic device including the same
Publication Date: 2021.04.20 DONGBU HITEK CO LTD
  • US10985754B1 patent drawing
  • US10985754B1 patent drawing
  • US10985754B1 patent drawing

AI summary

An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.