Flash Threshold Logic Gates With Programmable Floating-Gate Weights
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Solution Overview
Problem
Conventional CMOS-based logic circuits face limitations in optimizing performance, power, and area (PPA) improvements, and threshold logic has been outside mainstream VLSI design due to lack of design tools and incompatibility with existing methodologies.
Innovation Solution
The introduction of flash threshold logic (FTL) using floating gate transistors allows for a novel circuit topology to realize complex threshold functions, enabling fine-grained weight selection and programming through a modified perceptron learning algorithm, which improves area, power, and performance compared to CMOS standard-cell implementations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS-based logic circuits are used, then compatibility with existing design methodologies is maintained, but performance, power, and area optimization opportunities are exhausted
Solution Approach 1:
The patent segments the logic circuit functionality by introducing a dedicated threshold logic unit with floating gate transistors that operates alongside or instead of conventional CMOS logic. This segmentation allows threshold logic functions to be implemented separately, enabling PPA optimization in specific circuit blocks while maintaining compatibility with existing CMOS design methodologies for other parts of the system.
2Productivity
If threshold logic gates are implemented using emerging devices, then PPA improvements can be achieved, but design tool compatibility and manufacturability remain problematic
Solution Approach 1:
The patent changes the key parameter of transistor threshold voltage by using floating gate transistors, which allow continuous adjustment of the threshold voltage parameter. This enables precise control over logic thresholds and weight values in neural network implementations, achieving superior PPA performance while the underlying transistor technology remains compatible with standard semiconductor manufacturing processes.
3Adaptability or versatility
If pNAND architecture is used for threshold gates, then integration with standard-cell ASIC design is enabled, but the number of implementable threshold functions is severely limited
Solution Approach 1:
The patent creates a universal threshold logic cell using floating gate transistors that can implement any threshold function by programming the threshold voltage of the floating gate devices. This universal cell structure replaces the function-limited pNAND architecture, enabling a single cell design to perform diverse threshold logic operations including AND, OR, NAND, NOR, and custom threshold functions, thereby achieving multi-functionality without increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
FTL cells exhibit significant improvements in area (73.3%), power (63.8%), and performance (17.7%) while being robust against process, voltage, and temperature variations, and can be used in conjunction with static CMOS standard-cell designs.
Implementation Method 1
FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables
Data Source
AI summary
Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.