Buffer Circuitry with Antiphase Inductor Arrangement for Clock Signal Matching
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Solution Overview
Problem
Existing buffer circuitry in high-speed clock signal generation and distribution paths, particularly in DAC and ADC applications, faces challenges in achieving precise matching due to threshold voltage variations in transistors, leading to performance mismatches and errors in clock signal delays.
Innovation Solution
The implementation of a buffer circuitry with a current-control arrangement that defines bias currents for signal-path switches, independent of threshold voltage variations, and the use of inductor arrangements with diagonally opposite inductors producing antiphase magnetic fields to minimize magnetic interference and phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional buffer circuitry is used in clock signal generation, then the circuit can operate at high speeds, but threshold voltage variations in transistors cause performance mismatches and delay errors
Solution Approach 1:
A current control arrangement is introduced as an intermediary component between the power supply and the signal path switches. This arrangement provides controlled bias currents that compensate for threshold voltage variations in the transistors, thereby maintaining consistent switching performance across different channels while preserving high-speed operation
Solution Approach 2:
The bias current parameter is dynamically adjusted through the current control arrangement to compensate for threshold voltage variations. By changing the current parameter, the system maintains consistent switching characteristics despite manufacturing variations in transistor threshold voltages, achieving better performance matching without sacrificing speed
2Area of stationary object
If inductors are placed close together in buffer circuitry, then the circuit area is reduced, but magnetic interference between adjacent inductors causes phase errors
Solution Approach 1:
Adjacent inductors are configured to generate magnetic fields in opposite directions (antiphase). The harmful magnetic interference between closely-spaced inductors is converted into a beneficial cancellation effect, where the opposing magnetic fields neutralize each other, eliminating phase errors while maintaining compact circuit area
Solution Approach 2:
The inductors are arranged in an asymmetric alternating pattern where adjacent inductors have opposite orientations. This asymmetric configuration ensures that magnetic fields from adjacent inductors oppose each other, canceling out interference while allowing compact placement of multiple inductors in the circuit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the matching of buffer circuitry performance across channels, reducing delay mismatches to less than 100fs and minimizing phase errors, thereby enhancing the accuracy of clock signals in high-speed DAC and ADC operations.
Implementation Method 1
an inductor arrangement with diagonally opposite inductors producing magnetic fields in antiphase
Data Source
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AI summary
An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.