Buffer Die Test Interface Circuit for High-Frequency Memory Testing
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Solution Overview
Problem
High-frequency testing of semiconductor memory devices on a wafer requires expensive test devices, and existing methods are inefficient for low-cost high-frequency testing.
Innovation Solution
A semiconductor memory device configuration with a buffer die and multiple memory dies stacked through silicon vias (TSVs), equipped with a test interface circuit that converts low-frequency test signals into high-frequency internal signals, enabling efficient high-frequency testing at a lower cost by using a serializer to synchronize test signals with different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-frequency testing is performed on semiconductor memory devices on a wafer, then testing speed and bandwidth are improved, but test device cost increases significantly
Solution Approach 1:
The testing system is segmented into two functional parts: a low-cost external test device that generates base clock signals, and an internal frequency multiplication circuit within the semiconductor device that generates high-frequency test signals. This segmentation allows the expensive high-frequency generation function to be moved from the test device to the semiconductor device itself, resolving the contradiction between testing speed and test device cost.
Solution Approach 2:
A phase-locked loop (PLL) circuit acts as an intermediary between the low-frequency base clock signal from the test device and the high-frequency test signals needed for memory testing. The PLL multiplies the input frequency by an integer factor P, enabling high-frequency testing while the test device operates at lower, more economical frequencies.
2Adaptability or versatility
If the number of pads is increased to support full command sets for high-frequency testing, then testing capability is improved, but device area and complexity increase
Solution Approach 1:
The test interface circuit is designed to perform multiple functions through a single unified structure. It can operate in different modes (normal mode and test mode) and support different command sets by internally generating expanded command sequences from a reduced set of external test signals, eliminating the need for separate dedicated pads for each command function.
Solution Approach 2:
The system changes operational parameters dynamically based on mode selection. In test mode, the PLL is enabled and operates at frequency P times the base clock, allowing high-frequency testing with reduced pad requirements. In normal mode, the PLL is disabled and the device operates with standard timing and full pad functionality, thus adapting to different operational requirements without permanent structural changes.
Data Source
AI summary
An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.