Buffer Electrode Pattern for Variable Resistive Memory Reset Current
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the size and increasing the performance of variable resistive memory devices, particularly in optimizing the structure and materials of electrode patterns to minimize reset current and dynamic resistance.
Innovation Solution
The semiconductor device incorporates a buffer electrode pattern with varying thickness regions, a lower electrode pattern with asymmetrical structures, and a trim insulating pattern to reduce contact area and resistance, along with a silicide pattern for ohmic contact, to enhance the heating effect and reduce reset current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the electrode pattern size is reduced to decrease device size, then integration density is improved, but reset current and dynamic resistance increase
Solution Approach 1:
The buffer electrode pattern is designed with varying thickness: a first region with greater thickness adjacent to the lower electrode pattern and a second region with lesser thickness adjacent to the variable resistive pattern. This local variation in thickness allows the electrode to provide lower resistance where needed (thicker region) while maintaining overall compact dimensions (smaller device size), thus resolving the contradiction between device size reduction and reset current control.
2Volume of moving object
If the electrode pattern size is reduced to decrease device size, then integration density is improved, but dynamic resistance increases
Solution Approach 1:
The buffer electrode pattern employs non-uniform thickness distribution with a thicker first region adjacent to the lower electrode pattern. This localized thickness increase reduces the resistance path in the critical region, thereby decreasing dynamic resistance while the overall compact structure maintains reduced device size.
3Reliability
If the contact area between electrode patterns is increased to reduce resistance, then dynamic resistance is reduced, but device size increases
Solution Approach 1:
Instead of increasing contact area in the planar dimension, the buffer electrode pattern increases thickness in the vertical dimension. This dimensional transition allows the electrode to provide lower resistance through increased cross-sectional area in the thickness direction while maintaining compact lateral dimensions, thus reducing dynamic resistance without increasing device footprint.
Solution Approach 2:
The buffer electrode pattern features a first region with greater thickness specifically positioned adjacent to the lower electrode pattern. This localized thickness increase creates a low-resistance path at the critical interface region, reducing dynamic resistance without requiring overall enlargement of the device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the reset current and dynamic resistance, allowing for improved performance and integration density in variable resistive memory devices.
Implementation Method 1
a silicide pattern disposed on the diode in the first hole
Implementation Method 2
The buffer electrode pattern including a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness
Data Source
AI summary
A semiconductor device includes a switching device disposed on a substrate. A buffer electrode pattern is disposed on the switching device. The buffer electrode pattern includes a first region having a first vertical thickness, and a second region having a second vertical thickness smaller than the first vertical thickness. A lower electrode pattern is disposed on the first region of the buffer electrode pattern. A trim insulating pattern is disposed on the second region of the buffer electrode pattern. A variable resistive pattern is disposed on the lower electrode pattern.