Buffer Inductor Placement for Parasitic Impedance Reduction
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Solution Overview
Problem
Conventional inductor-tuned buffer circuits face challenges in accurately modeling and designing due to parasitic impedances, leading to shifts in resonance frequency and increased power consumption, requiring complex and time-consuming modeling of parasitic inductances and resistances.
Innovation Solution
The buffer inductors are moved closer to capacitive loads to reduce parasitic inductances and resistances, allowing for a more robust design that is less sensitive to parasitic impedances, enabling precise tuning without the need for highly accurate models and resulting in reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If buffer inductors are placed far from capacitive loads, then circuit layout is simplified, but parasitic inductances and resistances increase causing resonance frequency shifts and increased power consumption
Solution Approach 1:
The patent applies preliminary action by proactively compensating for parasitic effects through design. Specifically, the buffer inductor values are pre-calculated to account for expected parasitic inductances and resistances of interconnecting conductors, allowing the circuit to achieve desired resonance frequency despite the presence of parasitics. This is done before actual parasitic measurements are taken.
Solution Approach 2:
The patent applies parameter changes by adjusting buffer inductor values based on parasitic characteristics. The design process involves calculating modified inductor values that compensate for parasitic effects, thereby changing the nominal inductor parameters to achieve the target resonance frequency while maintaining layout simplicity.
2Measurement precision
If highly accurate models of parasitic inductances and resistances are used, then resonance frequency tuning precision is improved, but design complexity and time consumption increase
Solution Approach 1:
The patent applies partial action by using simplified parasitic models that capture the dominant effects without requiring complete accuracy. Instead of modeling all parasitic elements in detail, the design focuses on compensating for the most significant parasitic inductances and resistances, achieving sufficient tuning precision without excessive modeling complexity.
Solution Approach 2:
The patent applies parameter changes by using empirical or approximate parasitic parameter values rather than highly accurate measured models. This allows the design process to proceed with reasonable precision while avoiding the time-consuming task of creating and implementing highly accurate parasitic models.
3Use of energy by moving object
If interconnect resistances are present, then power consumption increases, but reducing interconnect resistance requires shorter conductors which limits layout flexibility
Solution Approach 1:
The patent applies parameter changes by calculating and selecting buffer inductor values that compensate for the power loss effects of interconnect resistances. This allows the use of longer interconnect conductors for layout flexibility while maintaining acceptable power consumption through proper inductor tuning that accounts for the resistive losses.
Solution Approach 2:
The patent converts the harmful effect of interconnect resistances into a design parameter. Rather than viewing parasitic resistances as purely detrimental, the design process incorporates them into the inductor value calculations, allowing the circuit to achieve optimal performance despite the presence of resistive losses in the interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a stable and high-impedance output with reduced sensitivity to parasitic impedances, enabling precise resonance frequency tuning and significant power savings by minimizing the impact of parasitic inductances and resistances.
Implementation Method 1
The tuning is performed by estimating the total capacitive load to be driven by the buffer circuit and using appropriate buffer inductance values to achieve a desired resonance frequency, coinciding with the clock signal frequency. Since the buffer circuit provides high impedance when operating at the resonance frequency
Data Source
AI summary
According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the buffer circuit. The buffer circuit is utilized to drive a capacitive load through an interconnecting conductor, where the buffer inductor is situated in proximity to the capacitive load so as to cause a parasitic inductance of the interconnecting conductor to be less than, or much less than, the buffer inductor.