Input/Output Impedence Modification TRIZ Cases
- Pass Switch Impedance Tuning for Lower Jitter and Attenuation
Sized impedance and faster gate activation cut pass-transistor jitter and high-frequency attenuation in broadband signal paths.
- Follower Output Buffer for Adaptive Transmission Line Impedance
A follower circuit adapts output impedance during switching to match transmission lines and reduce supply noise, ringing, and ISI.
- Single-Ended Input Buffer With Capacitive Symmetry Boost
Capacitive coupling lets a differential input buffer mimic the opposite reference transition, improving symmetry and speed for single-ended signals.
- Transmitter Pad Transition Control Using Pre-Charged Capacitors
Pre-charged capacitors shape transmitter rise and fall times to balance EMI, receiver performance, and reflections without extra timing control.
- Variable-Width Driver Circuit for Glitch-Reduced Impedance Matching
Synchronized combined control signals adjust transistor width at clock edges to keep driver impedance stable and reduce glitches and reflections.
- Linear Output Driver Circuit for Constant Impedance Across Voltage
Parallel transistor legs linearize driver current over voltage, keeping output impedance stable and reducing mismatch noise in memory I/O.
- ZQ Calibration Circuit for Fast, Precise Memory Termination Matching
A two-stage ZQ calibration circuit uses normal and micro target ranges to speed resistance tuning while improving memory termination accuracy.
- Variable Impedance Sensing With Offset-Compensated Matching
Offset polarity detection adjusts VIS matching codes to cut input-offset error and improve impedance accuracy at low supply voltage.
- Distributed On-Die Termination for Memory Signal Integrity
Segmenting termination across multiple memory dies reduces parasitic capacitance while maintaining impedance matching for high-speed data signals.
- Embedded Resistor Calibration for IC Buffer Circuits
A calibration module with a multiplexor connects a single embedded resistor to multiple buffer circuits, reducing component count and platform size.
- On-Chip Memory Impedance Calibration Without Extra Pins
Internal bias circuit mirrors current through adjustable resistor to calibrate IO impedance without extra package pins or off-chip components.
- Driver Circuit Impedance Adjustment for ESD Protection
Integrating impedance adjustment circuits with ESD protection reduces chip area while maintaining high-frequency signal integrity.
- Termination Voltage Circuit for Signal Reflection Reduction
A termination voltage circuit generates a matching node voltage to reduce signal reflection in driver circuits.
- Resistor Array With Short-Circuit Lines For Impedance Matching
Segmented resistors with switchable short-circuit lines enable precise impedance matching for transmission lines despite manufacturing variations.
- Semiconductor Memory I/O Circuit Load Control
A semiconductor memory input output circuit buffers data and controls signal line load via an enable signal.
- Active Load Generation Circuit for Impedance Stability
A transistor-based active load generation circuit adjusts impedance via a control voltage derived from input signals and reference voltages.
- SST Driver Electrostatic Protection via Dual Discharge Paths
Dual discharge modules route electrostatic currents through parallel paths to protect SST signal drivers.
- Multi-chip Package ZQ Calibration via Master-Slave Reference
Master chip establishes reference resistance values enabling simultaneous slave calibration to reduce total ZQ time.