Distributed On-Die Termination for Memory Signal Integrity

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Solution Overview

Problem

Existing memory systems face challenges in maintaining signal integrity due to impedance mismatches between different segments of transmission paths, leading to energy reflections and performance degradation, and current solutions like end-die signal termination increase parasitic capacitance and complicate manufacturing.

Innovation Solution

The use of a stack of uniform memory dies with on-die termination resistance circuits connected in parallel to provide a minimum termination resistance, ensuring effective impedance matching and reducing parasitic capacitance, allowing for efficient signal communication without the need for specially designed components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If end-die signal termination is used to address impedance mismatches, then signal integrity is improved, but parasitic capacitance on the IO signal increases

Engineering Contradiction:

Improvesignal integrityVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The termination function is segmented from a single end-die location and distributed across multiple memory dies along the transmission path. Each die contributes a portion of the total termination resistance, achieving the required signal integrity while reducing the parasitic capacitance burden on any single die's IO signal.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the transmission path are assigned different termination functions. Memory dies closer to the controller provide termination resistance, while the target die performs its primary memory function. This local differentiation optimizes both signal integrity and reduces parasitic capacitance effects.

Inventive Principle:

Principle #3Local quality

2Reliability

If specially configured electronic components are used for signal termination, then termination performance is improved, but manufacturing and assembly complexity increases

Engineering Contradiction:

Improvetermination performanceVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Uniform memory dies are designed to perform multiple functions: primary memory operations and signal termination. By integrating termination capability into standard memory die design, the system eliminates the need for specially configured termination components, simplifying manufacturing and assembly while maintaining termination performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses homogeneous uniform memory dies for both memory storage and termination functions. This eliminates the need for mixed-component assemblies with specialized termination devices, streamlining the manufacturing process and reducing quality control complexity while achieving effective termination.

Inventive Principle:

Principle #33Homogeneity

3Speed

If multiple uniform memory dies are used in the transmission path, then bandwidth and frequency are increased, but impedance matching becomes more challenging

Engineering Contradiction:

Improvebandwidth and frequencyVSAvoidimpedance matching

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The termination resistance is segmented and distributed across multiple memory dies rather than concentrated at one location. This segmentation allows each die to contribute to the overall termination, maintaining impedance matching across the extended transmission path enabled by multiple high-speed dies.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances signal integrity by reducing impedance mismatches, increasing bandwidth and frequency, and simplifying manufacturing by using uniform memory dies, while minimizing parasitic capacitance and maintaining effective termination resistance.

Implementation Method 1

Each memory die of the comprises an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance.

Methodology Applied

Scientific EffectElectrical Resistance: Electrical Resistance

Implementation Method 2

The stack of uniform memory dies is coupled to a transmission line by a set of wire bonds that connect each uniform memory die of the stack of uniform memory dies in series to form a transmission path.

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS11456022B2Distributed grouped terminations for multiple memory integrated circuit systems

Publication Date: 2022.09.27 SANDISK TECHNOLOGIES LLC

AI summary

The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.