Multi-chip Package ZQ Calibration via Master-Slave Reference
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Solution Overview
Problem
In multi-chip packages, the sequential ZQ calibration process for multiple memory chips is time-consuming due to the need for each chip to perform the calibration operation individually, leading to increased calibration time as the number of chips increases.
Innovation Solution
A method where a master chip performs a first ZQ calibration operation, and then slave chips perform simultaneous second ZQ calibration operations using termination resistance values set by the master chip, reducing the overall calibration time by completing the process in two stages instead of sequentially for each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential ZQ calibration is performed for each memory chip, then calibration accuracy is maintained, but calibration time increases significantly
Solution Approach 1:
The calibration process is segmented into two distinct phases: a first ZQ calibration operation performed by the master chip to establish reference termination resistance values, and second ZQ calibration operations performed by slave chips using those reference values. This segmentation allows parallel execution of multiple calibrations while maintaining accuracy through the master chip's reference measurements.
Solution Approach 2:
The master chip performs preliminary ZQ calibration operations first to determine accurate termination resistance values before the slave chips begin their calibration. This preliminary action by the master chip provides the reference data that enables subsequent slave chips to calibrate simultaneously without compromising measurement precision.
2Quantity of substance
If multiple memory chips are equipped in one package, then memory capacity increases, but the number of sequential calibration operations increases
Solution Approach 1:
Multiple slave chips merge their calibration operations and execute them simultaneously in parallel, rather than sequentially. The master chip coordinates this merged operation by providing reference termination resistance values that all slave chips can use concurrently, thereby maintaining high memory capacity while dramatically improving calibration efficiency.
Solution Approach 2:
Slave chips copy the termination resistance values determined by the master chip during its first calibration operation. This copying mechanism allows each slave chip to perform accurate calibration without repeating the entire measurement process, enabling parallel calibration across multiple chips and improving overall productivity.
3Reliability
If each memory chip performs independent ZQ calibration, then calibration accuracy is maintained, but waiting time for sequential calibration increases
Solution Approach 1:
The master chip acts as an intermediary that performs the time-consuming reference measurements first, then provides the determined termination resistance values to all slave chips. This intermediary role eliminates the need for each slave chip to independently perform full calibration sequences, maintaining reliability through accurate reference values while reducing waiting time through parallel execution.
Data Source
AI summary
A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.