SST Driver Electrostatic Protection via Dual Discharge Paths
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Solution Overview
Problem
Existing SST drivers face challenges in providing adequate electrostatic protection due to the fragility of thin gate oxide devices, leading to excessive capacitive loads and power consumption, especially during high-speed data transmission.
Innovation Solution
The SST driving circuit incorporates a dual electrostatic current discharge module with P-path and N-path protective units, including diodes and termination resistors, to create additional discharge paths and reduce the voltage burden on sensitive devices, enhancing electrostatic protection while minimizing the size of protective diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a P-type diode with larger size is used to reduce impedance for electrostatic protection, then electrostatic protection capability is improved, but capacitive load increases and signal integrity deteriorates
Solution Approach 1:
The patent divides the single diode protection path into multiple parallel paths (first discharge path through P-diode, second discharge path through N-diode, third discharge path through PMOS, fourth discharge path through NMOS). This segmentation allows current to be distributed across multiple smaller components rather than requiring one large diode, thereby maintaining protection capability while reducing individual component sizes and their associated capacitive loads.
Solution Approach 2:
The patent merges electrostatic protection functions with the existing drive circuitry by utilizing both P-type and N-type devices in the same circuit topology. The protective diodes and transistors are integrated with the termination resistors and signal paths, allowing simultaneous signal transmission and electrostatic discharge through shared circuit elements.
2Reliability
If a P-type diode with larger size is used to reduce impedance for electrostatic protection, then electrostatic protection capability is improved, but power consumption increases
Solution Approach 1:
The protection function is segmented across multiple smaller diodes and transistors rather than one large diode. Each component operates at lower current levels during normal conditions, reducing individual power consumption. The parallel architecture ensures that not all protective paths are fully activated simultaneously, distributing the energy burden.
Solution Approach 2:
The patent employs multiple smaller protective components that can be rapidly activated and deactivated. These components are designed to handle transient electrostatic events rather than continuous operation, allowing them to be optimized for low standby power consumption while providing robust protection during electrostatic discharge events.
3Speed
If thin gate oxide devices are used to achieve higher interconnect transmission speed, then transmission speed is improved, but electrostatic protection capability deteriorates
Solution Approach 1:
The patent segments the electrostatic discharge current across multiple parallel paths involving different device types (P-diodes, N-diodes, PMOS, NMOS). This distribution prevents any single thin-gate device from bearing the full electrostatic stress, thereby protecting vulnerable thin-gate oxide devices while maintaining high-speed transmission capabilities.
Solution Approach 2:
The patent introduces robust P-type and N-type diodes as intermediary protective elements between external electrostatic threats and the sensitive thin-gate oxide devices. These diodes act as first-line defenders that can handle high electrostatic currents, preventing direct stress on the vulnerable thin-gate transistors while allowing normal high-speed signal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the electrostatic protection capability, reduces capacitive loads, and improves signal transmission data rates while lowering power consumption, meeting the requirements for modern nanoscale CMOS processes.
Implementation Method 1
a current flows through the forward direction of a p-type diode, flows to power supply, and then when the power clamp circuit detects the increase of power supply voltage, a protection circuit of the power clamp is turned on, thereby discharging current to the ground
Implementation Method 2
V(diode)=0.7V+1.3 A*1 ohm=2.0V, where 0.7V is the forward-conducting voltage of the diode
Data Source
AI summary
The present disclosure provides an SST driving circuit, a chip, and a driving output method. The SST driving circuit includes: a signal driver for driving and outputting a signal to be driven, the signal driver including termination resistors; a first electrostatic current discharge module, providing first discharge paths for electrostatic currents generated in the signal driver; a second electrostatic current discharge module, connected in series with the termination resistors, providing second discharge paths for the electrostatic currents; and a power clamp, used for conducting the power clamp circuit, the first discharge paths and the second discharge paths when a power supply voltage of the signal driver exceeds a clamping voltage. The present disclosure provides different discharge paths, which effectively reduces voltage borne by a protected device through a voltage division method, and improves the device's ability to protect against electrostatic discharge.