Single-Ended Input Buffer With Capacitive Symmetry Boost
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Solution Overview
Problem
Differential input buffers in integrated memory devices often operate non-symmetrically when receiving single-ended input signals, leading to inconsistent responses to signal transitions and limited frequency capabilities compared to differential inputs.
Innovation Solution
Incorporating capacitive coupling between the gates of transistors in a differential input buffer circuit to mimic the operation of complementary signals, allowing the buffer to respond symmetrically to single-ended inputs by mimicking the transition of a reference signal in the opposite direction, thus enhancing symmetry and response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a differential input buffer uses a symmetrical structure with differential amplifiers, then it operates symmetrically when receiving complementary signals, but it responds slower to single-ended input signals compared to differential inputs
Solution Approach 1:
The patent applies asymmetry by introducing capacitive coupling only to one side of the differential amplifier structure when receiving single-ended inputs. Specifically, a capacitor couples the single-ended input signal to one gate of the differential pair, while the other gate receives the reference signal directly without capacitive coupling. This asymmetric configuration allows the buffer to achieve faster response times for single-ended inputs while maintaining the underlying symmetrical structure for differential operation.
2Adaptability or versatility
If a differential input buffer receives single-ended input signals, then it can be used with single-ended buses, but it operates in a non-symmetrical manner causing inconsistent responses to signal transitions
Solution Approach 1:
The patent uses capacitive coupling as an intermediary mechanism to bridge the single-ended input signal to the differential amplifier structure. The capacitor acts as a mediator that couples the single-ended input to one gate of the differential pair, enabling the buffer to accept single-ended inputs while maintaining symmetrical operation through the differential amplifier's inherent balance.
3Device complexity
If a differential input buffer uses conventional structure without capacitive coupling, then it has simpler circuit design, but it cannot achieve symmetrical response to single-ended input transitions
Solution Approach 1:
The patent changes the electrical parameters of the input buffer by introducing capacitive coupling. The capacitor modifies the impedance and signal transmission characteristics, enabling the differential amplifier to respond symmetrically to single-ended input transitions. This parameter change allows the circuit to achieve symmetrical operation without fundamentally redesigning the entire differential amplifier structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive coupling enables the input buffer to respond to single-ended input signal transitions in a symmetrical manner, achieving faster response times and higher frequency operation comparable to differential inputs.
Implementation Method 1
the capacitor couples a single-ended input signal to a gate of the transistor
Data Source
AI summary
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level.