Driver Circuit Impedance Adjustment for ESD Protection
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in providing effective Electrostatic Discharge (ESD) resistance due to the complexity of ESD discharge pathways and the need for reduced chip area, making it difficult to protect against ESD damage.
Innovation Solution
A driver circuit with integrated impedance adjustment circuits and ESD protection mechanisms, utilizing MOS transistors, diodes, and resistors to adjust impedance and protect against ESD events, while minimizing circuit area and transistor size to enhance ESD resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection circuits are added to protect against electrostatic discharge, then reliability against ESD damage is improved, but device complexity and chip area increase
Solution Approach 1:
The patent combines the ESD protection function with the existing impedance adjustment circuit by integrating ESD protection circuits at the output ends of the impedance adjustment circuits. This merging approach allows the ESD protection function to be added without creating a completely separate protection system, thereby improving ESD resistance while limiting the increase in device complexity.
Solution Approach 2:
The output pads and associated circuits are designed to serve multiple functions: impedance adjustment for signal integrity and ESD protection for reliability. By making the protection circuits universal and applicable to differential output circuits, the patent reduces overall system complexity while maintaining comprehensive ESD protection.
2Reliability
If ESD protection circuits are added to protect against electrostatic discharge, then reliability against ESD damage is improved, but chip area increases
Solution Approach 1:
The patent applies ESD protection locally at the output pads where ESD events are most likely to occur and cause damage. By placing ESD protection circuits specifically at the differential output circuit outputs rather than throughout the entire chip, the solution provides effective ESD resistance while minimizing the additional chip area required.
Solution Approach 2:
The impedance adjustment circuits use可变 impedance elements that can dynamically adjust their characteristics. This dynamic capability allows the same circuit structures to serve both impedance matching and ESD protection functions under different operating conditions, reducing the need for separate dedicated protection components and thereby minimizing chip area.
3Area of stationary object
If circuit area is reduced to minimize chip size, then manufacturing cost and chip area are improved, but ESD resistance deteriorates
Solution Approach 1:
The patent segments the ESD protection function into discrete protection circuits that are strategically placed at the output pads. This segmentation allows ESD protection to be implemented in a targeted manner rather than requiring comprehensive protection across the entire chip, thereby maintaining ESD resistance while minimizing overall chip area.
Solution Approach 2:
The ESD protection circuits are nested within the existing output circuit structure, utilizing the same output pads and interconnect structures. By nesting the protection function within the existing circuit architecture rather than adding external protection elements, the patent achieves effective ESD resistance without significant increases in chip area.
Data Source
AI summary
According to one embodiment, a first impedance adjustment circuit of a driver circuit includes a first resistor having an end connected to a first signal node. The first impedance adjustment circuit includes a first MOS transistor having an end connected to the other end of the first resistor. The first impedance adjustment circuit includes a second resistor having an end connected to the first signal node. The first impedance adjustment circuit includes a second MOS transistor having an end connected to the other end of the second resistor. The first impedance adjustment circuit includes a third resistor having an end connected to the other end of the first MOS transistor and the other end of the second MOS transistor, and the other end connected to the first output pad.