Buffer Placement in Hierarchical VLSI Designs
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Solution Overview
Problem
Current buffer placement algorithms in VLSI chip design fail to consider localized wiring contracts and geometry, leading to inefficiencies in wiring track utilization, as buffers with horizontal data flow are often placed in horizontal slots, conflicting with tracks used by buffers with vertical data flow.
Innovation Solution
The solution involves identifying buffers placed in slots oriented in the same direction as their data flow and relocating them to slots oriented perpendicular to the data flow, maximizing wiring track utilization by checking geometric orientations and aspect ratios of parent placement areas and adjusting buffer placements accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If buffers are placed in slots oriented in the same direction as their data flow, then placement is simplified, but wiring track utilization deteriorates due to conflicts with perpendicular tracks
Solution Approach 1:
The patent inverts the conventional buffer placement approach by deliberately placing buffers in slots oriented perpendicular to their data flow direction rather than parallel to it. This inversion resolves the wiring track conflict where horizontal data flow buffers were occupying horizontal slots, preventing vertical track usage. By inverting the placement orientation, the patent enables efficient use of both horizontal and vertical wiring tracks simultaneously.
Solution Approach 2:
The patent applies local quality by differentiating placement strategies based on the specific wiring contract requirements of each buffer location. Instead of a uniform placement rule, the system analyzes the localized wiring contracts and slot geometries to determine optimal buffer positions that maximize track utilization in each specific context, balancing data flow direction with slot orientation requirements.
2Productivity
If buffers are placed to maximize wiring track utilization, then wiring efficiency improves, but placement complexity increases due to geometric orientation analysis
Solution Approach 1:
The patent applies preliminary action by pre-defining slot geometries and wiring contracts before buffer placement occurs. The placement algorithm uses these pre-established geometric constraints and wiring requirements to automatically determine optimal buffer positions, avoiding the need for complex real-time calculations during the placement process itself.
Solution Approach 2:
The patent implements feedback mechanisms where the placement algorithm continuously monitors wiring track usage and slot orientation relationships, adjusting buffer placements based on detected conflicts or optimization opportunities. This feedback loop enables the system to learn from previous placement decisions and improve track utilization without requiring exhaustive search algorithms.
3Productivity
If localized wiring contracts are considered in buffer placement, then wiring track efficiency improves, but placement time increases
Solution Approach 1:
The patent segments the chip layout into distinct placement areas with defined wiring contracts and slot geometries. By dividing the complex placement problem into manageable segments, each with its own wiring requirements and geometric constraints, the algorithm can process and optimize placement locally without requiring comprehensive analysis of the entire chip design, thereby reducing overall placement time.
Data Source
AI summary
A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.