Buffer Redundancy for Error Detection

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Solution Overview

Problem

Existing data processing systems face challenges in effectively testing buffer entries for errors due to their design and operational characteristics, which makes it difficult to detect faults in buffers, especially in high-performance processors where error detection mechanisms are costly and complex to implement.

Innovation Solution

The implementation of a redundant allocation mode in buffer control circuitry, where items are allocated to multiple redundant entries of the buffer, allowing for error detection by comparing items stored in these entries and triggering an error handling response when mismatches are found, thereby simplifying fault testing and reducing the complexity of software self-test sequences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software-based testing is used to detect buffer errors, then error detection capability is improved, but the complexity of designing test sequences increases significantly

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcomplexity of designing test sequences
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies copying by creating redundant copies of buffer entries. Each buffer entry is replicated multiple times (e.g., three copies) and the same data is written to all copies. During testing, the system reads from all copies and compares the values to detect errors. This copying approach simplifies testing because the same test sequence can detect errors in multiple buffer entries simultaneously, eliminating the need for complex sequences to probe every possible error location individually.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent segments the buffer into redundant sets where each buffer entry is divided into multiple copies. This segmentation allows the testing mechanism to treat multiple buffer entries as a single test unit, reducing the number of separate test operations needed. The segmentation is implemented through the redundant allocation mode where buffer control circuitry manages multiple copies of the same data, enabling simplified test sequences that work across all segmented portions.

Inventive Principle:
Principle #1Segmentation

2Reliability

If redundant allocation mode is implemented with multiple redundant entries, then error detection capability is improved, but the buffer capacity and processing performance are reduced

Engineering Contradiction:
Improveerror detection capabilityVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamics by providing a mode-switching mechanism that allows the buffer control circuitry to transition between normal operation mode and redundant allocation mode. During normal operation, the buffer operates with full capacity for maximum processing performance. During testing, the system switches to redundant allocation mode to enable error detection. This dynamic switching allows the system to optimize for performance during operation and for reliability during testing without compromising either aspect permanently.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies periodic action by implementing testing at specific intervals or under specific conditions rather than continuously. The redundant allocation mode is activated periodically for testing purposes while normal processing continues uninterrupted. This periodic testing approach allows the system to maintain high processing performance during normal operation while still achieving comprehensive error detection capability through periodic verification of buffer integrity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11113164B2Handling errors in buffers
Publication Date: 2021.09.07 ARM LTD
  • US11113164B2 patent drawing
  • US11113164B2 patent drawing
  • US11113164B2 patent drawing

AI summary

A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.