Buffered 3D Capacitor Structure to Prevent Edge Shorting
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Solution Overview
Problem
Existing methods for forming capacitors and ionic capacitors within porous 3D structures face issues such as electrical shorting due to non-selective etching, which damages thin dielectric or ionic conductor layers, especially when using solid-state electrolytes like LiPON, leading to irregular surfaces and reduced capacitance density.
Innovation Solution
Incorporating a buffer layer of insulating material between the intermediate and bottom electrode layers or between the intermediate and top electrode layers, with an opening that defines a central active region, preventing electrical shorting by spacing them apart and allowing conformal deposition of the electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SF6 etching is used to define the edge of the top electrode layer, then the electrode edge can be delimited, but the intermediate layer (especially thin layers <20nm) is damaged causing electrical shorting and irregular surfaces
Solution Approach 1:
A buffer layer of inert material (such as silicon oxide or silicon nitride) is introduced between the top electrode layer and the intermediate layer. This buffer layer acts as a mediator that protects the intermediate layer from damage during SF6 etching while still allowing the etching process to define the electrode edge. The buffer layer is selectively removed after etching to complete the structure.
Solution Approach 2:
The buffer layer is deposited on the intermediate layer before the etching process begins. This preliminary action creates a protective barrier that prevents the subsequent SF6 etching from damaging the intermediate layer, allowing the etching to proceed safely to define the electrode edge without compromising layer integrity.
2Quantity of substance
If the thickness of the dielectric or ionic conductor layer is reduced to increase capacitance density, then energy storage density improves, but the layer becomes more susceptible to etching damage and electrical shorting
Solution Approach 1:
The buffer layer serves as a protective intermediary that enables the use of extremely thin intermediate layers (less than 20nm) for high capacitance density while preventing etching damage. The buffer layer absorbs the mechanical and chemical stress of the etching process, allowing thin intermediate layers to maintain their integrity throughout manufacturing.
3Quantity of substance
If conformal deposition is used to maximize capacitance utilization, then energy storage efficiency improves, but the deposition process becomes more complex on contoured surfaces
Solution Approach 1:
The buffer layer is selectively positioned in specific regions where it is needed for protection during etching, rather than being applied uniformly throughout the structure. This local application simplifies the overall deposition process while still providing the necessary protection in critical areas, balancing capacitance utilization with process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents electrical shorting and maintains capacitance density by ensuring selective etching, even with thin layers, thereby preserving the integrity of the capacitor structure.
Implementation Method 1
the intermediate layer is spaced apart from either the bottom electrode layer or the top electrode layer by a buffer layer in a peripheral region that surrounds the central region
Implementation Method 2
The porous structure may result from the anodization of a thin layer of aluminum deposited above the substrate (e.g. deposited on the substrate or deposited on one or more layers which are themselves formed on the substrate). The anodization process converts the AI into alumina, which is porous (PAA).
Implementation Method 3
the SF6 used to etch the top electrode (typically TiN) can react with the lithium within the LiPON layer and may lead to creating an irregular surface having the aspect of grass
Data Source
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Figure 5~6
AI summary
An integrated electrical device comprising an energy storage component, the component comprising, above a support (100, 101, 103), a bottom electrode layer (105), an intermediate layer (107) comprising a dielectric layer or an ionic conductor layer above the bottom electrode layer, and a top electrode layer (108) above and on the intermediate layer, wherein the intermediate layer is in contact with the bottom electrode layer and with the top electrode layer in a central region (CR), and the intermediate layer is are spaced apart from either the bottom electrode layer or the top electrode layer by a buffer layer (106) in a peripheral region (PR) that surrounds the central region, the buffer layer comprising an insulating material and being arranged on the bottom electrode layer or on the intermediate layer, the buffer layer having an opening that opens onto the bottom electrode layer or onto the intermediate layer so as to define the central region, the intermediate layer and the top electrode layer being arranged conformally above the bottom electrode layer.