Build-up Circuit Board with Etching Stop Layers
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Solution Overview
Problem
The challenge in the electronics industry is to create circuit boards with smaller trace pitches and thicknesses while maintaining high integration and performance, which existing manufacturing methods struggle to achieve effectively.
Innovation Solution
A method involving the formation of sacrificial metal layers, etching stop layers, and build-up structures on a carrier, using materials like tin, titanium, or aluminum to control metal bump dimensions and prevent alkaline etching damage, allowing for increased circuit layer space and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pitch of traces is reduced to achieve higher integration, then the integration density is improved, but the manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent divides the circuit board structure into multiple layers with circuit patterns on both front and back surfaces, interconnected through vias. This segmentation allows independent optimization of each layer's trace pitch while maintaining overall manufacturing feasibility, resolving the contradiction between high integration density and manufacturing precision.
Solution Approach 2:
The patent transitions from a single-sided circuit board to a double-sided or multi-layer structure, adding the vertical dimension through vias and interlayer connections. This dimensional change enables higher integration density without requiring excessively small trace pitches on individual layers, thus maintaining manufacturing precision.
2Length of stationary object
If the thickness of circuit board is reduced to achieve miniaturization, then the size is improved, but the structural stability and reliability worsen
Solution Approach 1:
The patent employs composite material structures including dielectric layers, conductive layers, and via structures with different material properties. This composite approach allows optimization of mechanical strength and electrical performance independently, enabling thin board design while maintaining structural stability and reliability through carefully selected material combinations.
3Ease of manufacture
If conventional manufacturing methods are used to maintain simplicity, then the ease of manufacture is improved, but the circuit layer space and yield worsen
Solution Approach 1:
The patent implements preliminary actions in the manufacturing process, such as forming via holes and depositing conductive materials before completing the circuit pattern formation. This preliminary structuring creates a framework that guides subsequent manufacturing steps, improving both space utilization and yield while maintaining reasonable process simplicity through standardized sequential operations.
Solution Approach 2:
The patent introduces intermediary structures such as solder resist layers, silkscreen layers, and protective coatings that mediate between the conductive circuit elements and the external environment. These intermediary layers enable better space utilization by allowing tighter routing while maintaining ease of manufacture through well-established deposition and patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the space for the circuit layer, prevents defects like cavities, and ensures reliable connections, enhancing the miniaturization and performance of circuit boards.
Implementation Method 1
performing a first etching process to remove the first sacrificial metal layer; and performing a second etching process to remove the first etching stop layer and the second etching stop layer
Data Source
AI summary
A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.