Lithography/Patterning TRIZ Cases

Vertical traces through openings raise I/O density without enlarging or thickening the substrate, helping maintain yield and limit warpage.

A grounded coaxial via layout removes insulating-layer mismatch to improve high-frequency signal integrity and EMI shielding.

A solid electrolyte membrane replaces resin resist to plate fine wiring with stronger seed-layer adhesion, fewer steps, and less liquid waste.

Photolithography, electrolytic plating, and polishing replace laser drilling to form 14 μm vias and 30–50 μm pitch in multi-layer boards.

A jig imprint-etches the conductive layer to form circuit patterns without lithography, cutting process complexity, defects, and cost.

Long-axis grooves in the bending region release stress and let a rigid circuit board bend to larger angles without damage.

Local IR heating over a smaller resist area cuts UV fluence and exposure time while limiting thermal distortion in direct imaging.

This case uses a release layer and overlapping openings to distribute warpage stress, improve adhesion, and support manufacturing yield.

A multilayer carrier foil design with a chromium release layer improves peeling consistency for ultra-thin copper applications.

Rolling mask lithography produces seamless metal mesh with submicron linewidths, eliminating seam lines from cylindrical mask lamination.

Surrounding the signal path with a conductive ground path eliminates EMI shielding gaps and impedance mismatch in high-frequency circuit boards.

Transparent PCB employs a hardened layer and low-temperature conductive paste to prevent thermal damage during component attachment.

Segmented dielectric layers with distinct constants surround a conductive via to eliminate impedance mismatch and reduce noise interference.

A circuit board manufacturing method uses aluminum paste and a selective etchant to form conductors on silicon substrates.

Electroless plating forms circuit patterns directly on metal housings, merging structural and electrical functions to reduce assembly space.

A two-layer insulating film structure levels surface protuberances on wiring boards, preventing valleys that trap air bubbles and weaken adhesive bonding.

Sacrificial metal and etching stop layers control bump dimensions, preventing alkaline etching damage while increasing circuit layer space.

Pulsed electromagnetic emission sinters metal oxide dispersions into conductive traces, bypassing high-temperature processing limits.

A circuit board manufacturing method uses a cured photosensitive dielectric layer to align subsequent metal layers.

A printed wiring board laminate uses controlled metal layer crystal orientation to enhance circuit formability.

A transparent conductive film uses a specific metal wiring surface shape to reduce specular reflectance.

Segmented thermoplastic insulation protects silicon carbide modules from heat damage while maintaining electrical performance.

Patterned conductive layers eliminate metal bridging to resolve electrostatic breakdown and whitening while maintaining high transmittance.

A water-soluble polymer layer defines circuit grooves for conductive filling and aqueous removal.