Lithography/Patterning TRIZ Cases
- Stacked Circuit Structure for High-Density I/O Without Substrate Warpage
Vertical traces through openings raise I/O density without enlarging or thickening the substrate, helping maintain yield and limit warpage.
- Coaxial Via Circuit Board Layout for Impedance Matching and EMI Shielding
A grounded coaxial via layout removes insulating-layer mismatch to improve high-frequency signal integrity and EMI shielding.
- Wiring Board Plating With Solid Electrolyte Membrane for Fine-Line Adhesion
A solid electrolyte membrane replaces resin resist to plate fine wiring with stronger seed-layer adhesion, fewer steps, and less liquid waste.
- Multi-Layer Circuit Board Vias Using Plated Metal Pillars
Photolithography, electrolytic plating, and polishing replace laser drilling to form 14 μm vias and 30–50 μm pitch in multi-layer boards.
- Circuit Board Patterning by Imprint-Etching Without Lithography
A jig imprint-etches the conductive layer to form circuit patterns without lithography, cutting process complexity, defects, and cost.
- Grooved Rigid-Flex Circuit Board for High-Angle Bending
Long-axis grooves in the bending region release stress and let a rigid circuit board bend to larger angles without damage.
- Resist Patterning with Local Heating for Faster UV Imaging
Local IR heating over a smaller resist area cuts UV fluence and exposure time while limiting thermal distortion in direct imaging.
- Electronic Device Circuit Structures with Release-Layer Warpage Relief
This case uses a release layer and overlapping openings to distribute warpage stress, improve adhesion, and support manufacturing yield.
- Multilayer Carrier Foil for Consistent Peeling and Pinhole Prevention
A multilayer carrier foil design with a chromium release layer improves peeling consistency for ultra-thin copper applications.
- Transparent Metal Mesh via Rolling Mask Lithography
Rolling mask lithography produces seamless metal mesh with submicron linewidths, eliminating seam lines from cylindrical mask lamination.