Electronic Device Circuit Structures with Release-Layer Warpage Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of electronic devices is hindered by warpage stress in circuit structures, leading to peeling and yield loss due to the accumulation of layers.
Innovation Solution
A method involving the use of a release layer on a substrate with a circuit structure, including conductive and insulating layers, where a first opening is formed to expose a portion of the insulating layer, followed by a second opening with a smaller width to distribute warpage stress and improve adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit structures and layers are piled up to increase functionality, then the device capability is improved, but warpage stress accumulates causing peeling and reducing manufacturing yield
Solution Approach 1:
The patent divides the continuous circuit structure into segmented regions by forming openings (via holes) through the insulating layers. These openings create discrete segments that can independently accommodate warpage stress, preventing stress accumulation across the entire structure. The circuit structures are separated into different regions (first circuit structure, second circuit structure) that can be independently managed for stress relief.
Solution Approach 2:
The patent introduces a release layer as an intermediary between the substrate and the circuit structures. This release layer acts as a stress buffer that absorbs and distributes warpage stress, preventing direct stress transmission to the circuit structures and reducing peeling. The release layer serves as a mediator that decouples the stress relationship between the substrate and the multi-layer circuit structures.
2Adaptability or versatility
If more layers are added to enhance device performance, then functionality is improved, but warpage stress increases causing peeling between layers
Solution Approach 1:
The patent segments the layered structure by forming openings through the insulating layers, creating discrete regions that prevent continuous stress accumulation across all layers. The openings divide the stacked layers into manageable segments that can accommodate differential expansion and contraction without causing inter-layer peeling.
Solution Approach 2:
The patent applies different properties to different regions of the structure. The release layer is selectively positioned beneath specific circuit structures, and openings are formed at strategic locations where stress concentration is expected. This localized approach allows the structure to maintain strong adhesion in critical areas while providing stress relief in other regions.
3Ease of manufacture
If circuit structures are disposed directly on the substrate, then manufacturing process is simplified, but warpage stress causes peeling and jeopardizes process yield
Solution Approach 1:
The patent introduces a release layer as an intermediary between the substrate and the circuit structures. This release layer is applied as a simple coating process that adds minimal manufacturing complexity while effectively reducing warpage stress and preventing peeling, thereby improving process yield without significantly complicating the manufacturing process.
Solution Approach 2:
The release layer is applied in advance, before the circuit structures are formed, to preemptively address the warpage stress issue. By preparing the stress-relief layer beforehand, the patent prevents peeling problems from occurring during subsequent processing steps, ensuring high process yield without requiring complex corrective measures later.
4Reliability
If openings are formed with different widths in overlapping pattern, then warpage stress is distributed effectively, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the opening structure into multiple levels with different widths (first opening, second opening with smaller width). This segmentation creates a stepped pattern that effectively distributes stress while providing tolerance for alignment variations. The overlapping but non-identical dimensions of the openings at different levels reduce the precision requirements compared to requiring perfect alignment of identical openings.
Solution Approach 2:
The patent employs asymmetric opening dimensions where the second opening has a smaller width than the first opening. This asymmetric design creates an overlapping pattern that is inherently more tolerant to alignment variations, as the staggered dimensions provide a buffer zone that accommodates manufacturing tolerances while still achieving effective stress distribution.
Data Source
AI summary
A release layer is on s substrate, and a circuit structure on the release layer. Providing the circuit structure includes a first conductive layer on the release layer, a first insulating layer on the first conductive layer and the release layer, a second conductive layer on the first insulating layer to electrically connect the first conductive layer through the via of the insulating layer, and a second insulating layer on the second conductive layer. A first patterning step is performed on the second insulating layer to form a first opening exposing the first insulating layer. A second patterning step is performed on the first insulation layer to form a second opening. In a cross-section of the electronic device, the second opening overlaps the first opening, the first opening width is smaller than the second opening width, the first opening exposes the surface of the first insulating layer.