Built-in Test Circuit for Semiconductor Wafer Testing
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Solution Overview
Problem
Semiconductor apparatuses at the wafer level are limited by the number of usable pads or pins, restricting the number of signals that can be input from external test equipment during wafer level testing, which hampers efficient testing and increases testing time.
Innovation Solution
A built-in self test circuit that utilizes a limited number of control signals from an external device to perform both burn-in stress and normal operation tests, including a first and second address buffer group, a test control block, and a self test address generation block to generate additional test signals internally, allowing for more comprehensive testing without additional design changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external test equipment is used to perform comprehensive tests at wafer level, then testing coverage may be improved, but the limited number of pads or pins restricts the number of signals that can be input, thereby limiting test capability
Solution Approach 1:
The test circuit generates its own test signals internally using a signal generation unit that creates address signals, command signals, and data signals without requiring external test equipment to provide all signals. This self-service approach allows the circuit to perform comprehensive tests despite having limited external signal inputs through the pads or pins
Solution Approach 2:
The test circuit is designed to perform multiple test functions including normal operation tests and burn-in stress tests using the same limited set of pads or pins. By internally generating different types of test signals and modes, the circuit achieves multi-functionality without requiring separate physical interfaces for each test type
2Measurement precision
If more signals are input from external test equipment to enable comprehensive testing, then testing precision may be improved, but the number of usable pads or pins is limited, preventing additional signal inputs
Solution Approach 1:
The test circuit segments the signal generation function by dividing it into internal signal generation for address signals, command signals, and data signals, versus external signal input only for enable signals. This segmentation allows comprehensive testing precision to be achieved by generating most signals internally, while using the limited external pads or pins only for essential control signals
3Productivity
If built-in self test circuits are implemented to overcome pad limitations, then test efficiency is improved, but the circuit design becomes more complex
Solution Approach 1:
The signal generation unit is merged with the existing test circuit structure, combining signal generation functions with the address buffer group and other test components. This merging approach improves test efficiency by enabling comprehensive built-in testing while minimizing the increase in overall circuit design complexity through integrated rather than separate implementations
Data Source
AI summary
A semiconductor apparatus includes first and second address buffer groups. The first address buffer group receives first address signals from an external source and outputs the first address signals to a first internal circuit, in first and second operation modes. The second address buffer group receives second address signals from the external source and outputs the second address signals to the first internal circuit, in the first operation mode, and receives third address signals which are generated in a second internal circuit and outputs the third address signals to the first internal circuit, in the second operation mode.