Digital Storage TRIZ Cases

Assist circuits detect resistive-open and bridging defects masked by voltage scaling, improving test coverage while minimizing area overhead.

A semiconductor device latches internal control signals using a dedicated circuit to generate alignment pulses for training operations.

A memory controller optical transmission unit generates complementary optical modulation signals using a coupler to split and couple light paths.

Generic physical interfaces on a configurable die support LPDDR3 and LPDDR4 without additional routing layers, reducing retrofit costs.

An airgap located directly above the phase change material layer provides space for expansion and restriction, mitigating damage from rigid walls.

Precharge circuits apply voltage to output data lines before sense amplifiers drive signals, reducing parasitic capacitance effects and enhancing reading speed.

A nonvolatile storage device uses self-reference reading with constant current to stabilize resistance states.

A row hammer refresh address calculation circuit identifies memory cells using minimal bit inversion operations to optimize semiconductor memory device performance.

Germanium-rich GST alloys stabilize differential stoichiometries in active zones, maintaining retention under automotive thermal stress.

A memory bitcell uses hierarchical decoding to route common address portions to a single read port.

A clockless state machine synchronizes memory access using separate row and column strobes.

A dynamic phase shifter and staticizer circuit shifts phase memory signals using a clock domino and staticizer to produce stable outputs.

A ferroelectric capacitor-based nvSRAM cell integrates volatile SRAM with non-volatile memory for high-speed data access.

Reset pulses applied by the word driver control circuit reduce variations in subword line discharging rates while meeting precharge time requirements.

Error correction circuit generates corrected data and error flags to control write operations, resolving reliability deterioration at high transmission speeds.

Integrated logic within DRAM executes background tasks during operation gaps, lowering power usage while maintaining data access efficiency.

Gate circuits inactivate internal signals to reduce power consumption, allowing immediate restart without stopping the input buffer or clock signal.

A built-in self test circuit generates internal address signals using dual buffer groups to perform comprehensive wafer level testing.

A memory system uses a voltage regulator circuit to adjust cell voltage levels.

Coupling capacitance tracks wordline behavior without dummy arrays, reducing area overhead.

A memory controller design omits termination components from short control lines to reduce manufacturing costs and free up circuit board space.

Sequential far-to-near voltage application reduces leak current and consumption current during forming operations.

A microcontroller system enables memory operations when a reference current source reaches a substantial fraction of its target level.

Dynamic compensation circuits estimate keeper PFET degradation and adjust current to preserve speed without sacrificing design density.

A verification circuit adjusts writing current to reset phase change memory cells for accurate data storage.

Segmented word line drivers share isolation areas to shrink the PRAM core size while maintaining transistor stability and reducing current consumption.

A segmented SRAM cell isolates storage nodes from write voltages during read cycles to prevent data disturbance.

A voltage regulator circuit with a replica resistive storage element provides regulated voltages to multiplexer transistors.

A semiconductor memory voltage adjuster modifies back bias voltages to optimize access currents across varying temperatures.

A semiconductor memory input circuit generates internal signals and selectively outputs them based on rank configuration.

A storage device selects reference potentials from a memory group to generate a standard potential for data reading.

Separate register outputs block command signals to inactive ranks, reducing power consumption during high-speed memory access.

A refresh control device uses latch circuits to generate word line enable signals for independent bank operations.

A sense amplifier monitors sensing operation validity to generate self-time control signals.

Randomizing address latching timing equalizes word line access, minimizing row hammer effects and preventing data loss from coupling-induced refresh failures.

Dynamic write assist circuits detect memory cell disturbances, reducing power consumption by 20% and extending component lifetime.

A resistive memory device uses a switch circuit to route write and read word line voltages through a common power path.

A semiconductor memory data output circuit generates selection and timing signals to sequentially output serial data from parallel inputs.

A static random access memory operating voltage tuning method uses shmoo test plots to lower power consumption.

A crossbar-based apparatus uses a shared calibration circuit to determine parameters from output data for analog components.

Segmented clock generators optimize power and frequency for design for testability without impacting mission mode operations.

A control circuit generates a variable frequency row hammer refresh signal to protect stored data.

Shared resistors and error amplifiers reduce layout area and current consumption in semiconductor memory devices.

A non-volatile memory device partitions its cell matrix into dynamically modifiable subspaces for independent programming and erasure operations.

A hybrid memory cell architecture integrates memristors with CMOS transistors to store data via resistance switching.

Sharing charge between bitlines and write assist circuitry reduces read disturb by lowering charge injection into memory cells.