Semiconductor Memory Module Registers Block Unaddressed Rank Signals
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Solution Overview
Problem
Semiconductor memory modules consume excessive power due to unnecessary transmission of command/address signals to unaddressed memory chip ranks, exacerbated by increasing operating speeds.
Innovation Solution
A semiconductor memory module design featuring two registers that selectively transmit command/address signals only to active ranks, blocking signals to inactive ranks, thereby reducing power consumption and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If command/address signals are transmitted to all memory chip ranks in parallel, then all ranks can be addressed simultaneously, but power is wasted transmitting signals to unaddressed ranks
Solution Approach 1:
The patent extracts and removes the unnecessary transmission of command/address signals to unaddressed memory chip ranks. By using separate register outputs for each rank and enabling only the required ranks, the system eliminates wasted signal transmission to inactive ranks, thereby reducing power consumption while maintaining the ability to address multiple ranks simultaneously when needed.
Solution Approach 2:
The patent segments the single register output into multiple separate outputs (first output, second output, third output, fourth output) corresponding to different memory chip ranks. Each output can be independently enabled or disabled based on which rank is being accessed, allowing selective signal transmission to specific ranks rather than broadcasting to all ranks simultaneously.
2Speed
If operating speed of semiconductor memory modules is increased, then data processing capability is improved, but power consumption further increases
Solution Approach 1:
The patent extracts and eliminates the unnecessary power consumption associated with transmitting command/address signals to unaddressed ranks at high speeds. By disabling the register outputs corresponding to inactive ranks, the system removes the source of wasted energy while preserving the high-speed operation capability for actually accessed ranks.
3Adaptability or versatility
If command/address signals are transmitted to multiple ranks simultaneously, then memory access flexibility is improved, but unnecessary signal transmission to non-addressed ranks occurs
Solution Approach 1:
The patent segments the register outputs into four independent outputs (first, second, third, fourth outputs) that can be independently controlled. This segmentation enables flexible memory access by allowing any combination of ranks to be activated simultaneously while preventing power waste by keeping inactive rank outputs disabled, thus avoiding unnecessary signal transmission.
Solution Approach 2:
The patent implements dynamic control of register outputs where each output can be independently enabled or disabled based on the current memory access requirements. This dynamic configuration allows the system to adapt to different access patterns (single rank, dual rank, or all ranks) while minimizing power consumption by activating only the necessary outputs.
Data Source
AI summary
A semiconductor memory module (1) includes a circuit substrate (2), a first (100), a second (200), a third (300) and a fourth (400) rank of memory chips (3), a first register (10) and a second register (20). The first register (10) and the second register (20) each comprise a first input (11, 21) for receiving a respective chip select signal (CS0, CS2), a second input (12, 22) for receiving a respective other chip select signal (CS1, CS3) at least one third input (13, 23) for receiving command/address signals (CA), and at least one third output (16, 26). The at least one third output (16, 26) of the respective first (10) and second (20) register transmits the command/address signals (CA), if at least one of the respective chip select signal (CS0, CS2) received at the respective first input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3) received at the respective second input (12, 22) of the respective register (10, 20) is active, and blocks a transmission of the command/address signals (CA), if both the respective chip select signal (CS0, CS2) received at the respective first input (11, 21) of the respective register (10, 20) and the respective other chip select signal (CS1, CS3) received at the respective second input (12, 22) of the respective register (10, 20) are inactive.