Clockless State Machine DRAM Interface Latency Reduction
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Solution Overview
Problem
Conventional memory access systems suffer from increased latency and power consumption due to the need for separate FIFOs on both the DRAM and memory controller sides, which are redundant in close proximity memory arrangements like direct 3D stacked DRAMs, leading to complexity and inefficiency.
Innovation Solution
A clockless state machine on the DRAM side eliminates the need for internal DRAM FIFOs, using separate row and column strobes to synchronize memory access, reducing latency and power consumption by maintaining a point-to-point association between data lines and the memory controller, thereby eliminating the need for DRAM-side FIFOs and relying solely on the memory controller's clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate FIFOs are used on both DRAM and memory controller sides to synchronize memory access, then timing synchronization between commands and results is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the DRAM-side FIFO structure from the memory interface, retaining only the memory controller-side FIFO. This eliminates the complexity of synchronizing two clock domains while maintaining timing synchronization through the controller-side FIFO alone, which handles all necessary queuing and retiming operations.
Solution Approach 2:
The patent merges the timing synchronization function into a single FIFO structure located at the memory controller, combining what were previously two separate FIFOs (one at DRAM side, one at controller side) into one unified structure. This consolidation reduces overall device complexity while preserving the essential synchronization function.
2Reliability
If DRAM-side FIFOs are used to maintain timing synchronization, then data congestion is prevented, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming DRAM-side FIFO structure, extracting only the essential data flow control function and implementing it at the memory controller side. This eliminates redundant power consumption while maintaining adequate data flow control through the single remaining FIFO structure.
3Reliability
If multiple FIFOs are used for clock domain crossing, then timing synchronization is maintained, but latency increases
Solution Approach 1:
The patent merges the clock domain crossing synchronization into a single FIFO structure at the memory controller, eliminating the need for separate FIFOs at the DRAM side. This reduces the number of queuing stages and associated latency while maintaining proper clock domain synchronization through the unified FIFO structure.
Data Source
AI summary
A close proximity memory arrangement maintains a point to point association between DQs, or data lines, to DRAM modules employs a clockless state machine on a DRAM side of the memory controller-DRAM interface such that a single FIFO on the memory controller side synchronizes or orders the DRAM fetch results. Addition of a row address (ROW-ADD) and column address (COL-ADD) strobe reducing latency and power demands. Close proximity point to point DRAM interfaces render the DRAM side FIFO redundant in interfaces such as direct stacked 3D DRAMs on top of the logic die hosting the memory controller. The close proximity point to point arrangement eliminates the DRAM internal FIFO and latency scheme, resulting in just the memory controller internal clock domain crossing FIFOs.