Memory Clock Generators for DFT Mode Optimization
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Solution Overview
Problem
Existing system-on-a-chip (SOC) designs with large numbers of memories face challenges in testability, as memory failures can affect SOC operation, and current Design for Testability (DFT) approaches may not efficiently manage power and performance across different operational modes.
Innovation Solution
The implementation of separate clock generators for mission mode and DFT operations within a global control circuit, allowing for independent tuning of power, performance, and area (PPA) for each mode without impacting the other, and enabling or disabling the global clock to optimize setup and hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock generator is used for both mission mode and DFT operations, then device complexity is reduced, but power and performance cannot be independently optimized for each mode
Solution Approach 1:
The clock generator is segmented into separate mission mode clock generator and DFT mode clock generator, each independently optimized for its specific operational mode. This segmentation allows independent tuning of power, performance, and area parameters for each mode without compromising the other, directly resolving the contradiction between device complexity and mode-specific adaptability.
2Productivity
If the global clock is continuously enabled, then performance is maintained, but setup and hold times increase due to long routing distances
Solution Approach 1:
The global clock is enabled in advance of data arrival at long routing distances, allowing the clock signal to propagate through the entire routing path before data needs to be captured. This preliminary clock activation reduces setup and hold time requirements, enabling higher frequency operations without compromising reliability.
3Reliability
If DFT testing is performed on all memory banks, then reliability is improved, but power consumption increases
Solution Approach 1:
DFT testing is applied selectively to specific memory banks or regions that require testing, rather than uniformly across all memory banks. This local application of DFT testing maintains necessary reliability coverage while significantly reducing overall power consumption by keeping non-critical memory banks in low-power states during testing operations.
Data Source
AI summary
In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.