Wordline Tracking via Coupling Capacitance
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Solution Overview
Problem
Existing methods for tracking wordline behavior in memory compilers with self-timed internal clocks face challenges, such as increased area overhead and inaccurate tracking using dummy arrays or metal wires, which can lead to functional issues during read and write operations.
Innovation Solution
The implementation of coupling capacitance between the wordline and complementary bitlines, utilizing Miller capacitance in the memory cell's pass transistor, allows for accurate tracking of wordline behavior without a dummy array, thereby reducing area overhead and improving tracking accuracy during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy array is used to track wordline behavior, then tracking capability is provided, but area overhead is increased
Solution Approach 1:
The patent creates a simplified copy of the wordline driver circuitry directly in the periphery logic devices, rather than copying the entire dummy array. This copy replicates only the essential wordline driver behavior needed for tracking, significantly reducing the area required while maintaining tracking functionality.
Solution Approach 2:
The patent extracts only the critical wordline driver functionality from the full dummy array and implements it separately in periphery logic devices. This extraction allows the main array to be reduced or eliminated, achieving tracking capability with minimal area overhead.
2Area of stationary object
If metal wire and gate load with periphery logic devices are used to track wordline behavior, then area overhead is reduced, but tracking accuracy deteriorates
Solution Approach 1:
The patent modifies the parameters of periphery logic devices, specifically adjusting threshold voltages and sizing of transistors, to accurately replicate the electrical characteristics of the real wordline driver. This parameter tuning ensures that the simplified periphery implementation achieves accurate tracking without requiring a full dummy array.
Solution Approach 2:
The patent applies different design qualities to different parts of the periphery logic devices. Critical components that directly affect wordline behavior tracking are designed with higher precision and appropriate sizing, while less critical components use standard designs, optimizing the balance between accuracy and area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and accurate tracking of wordline behavior with minimal area overhead, enhancing the reliability of read and write operations in memory applications.
Implementation Method 1
The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.
Implementation Method 2
utilizing Miller capacitance in the memory cell's pass transistor
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.