Hierarchical Decoding for Single Read Port Memory Bitcells
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Solution Overview
Problem
Traditional SRAM memory bitcells require multiple read ports for accessing data, leading to increased area and power consumption due to the need for full address decoding and amplification of signals across large arrays.
Innovation Solution
Implementing hierarchical decoding of memory addresses to identify a common address portion, which is used to select a single read port in the memory bitcell, and a modified sense amplifier that receives decoded uncommon address portions to enable data output, reducing the number of read ports required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple read ports are implemented in the memory bitcell, then data access capability is improved, but area and power consumption increase
Solution Approach 1:
The patent segments the address decoding function into two parts: a first decoder that decodes a first portion of the address and a second decoder that decodes a second portion of the address. This segmentation allows the memory bitcell to use a single read port while still supporting multiple address spaces, as the combined decoding results determine which read port should be activated. This resolves the contradiction by maintaining data access capability through intelligent address segmentation rather than physically implementing multiple read ports.
Solution Approach 2:
The patent introduces a sense amplifier as an intermediary component that receives decoded address portions and uses them to selectively enable read ports. The sense amplifier acts as a mediator between the address decoding logic and the read ports, allowing a single read port to serve multiple address spaces by enabling or disabling the port based on the decoded address portions. This intermediary approach maintains data access capability while avoiding the need for multiple physical read ports in the memory bitcell.
2Ease of operation
If multiple read ports are implemented in the memory bitcell, then data access capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the address decoding function into two parts: a first decoder that decodes a first portion of the address and a second decoder that decodes a second portion of the address. This segmentation allows the memory bitcell to use a single read port while still supporting multiple address spaces, as the combined decoding results determine which read port should be activated. This resolves the contradiction by maintaining data access capability through intelligent address segmentation rather than physically implementing multiple read ports.
Solution Approach 2:
The patent introduces a sense amplifier as an intermediary component that receives decoded address portions and uses them to selectively enable read ports. The sense amplifier acts as a mediator between the address decoding logic and the read ports, allowing a single read port to serve multiple address spaces by enabling or disabling the port based on the decoded address portions. This intermediary approach maintains data access capability while avoiding the need for multiple physical read ports in the memory bitcell.
3Measurement precision
If full address decoding is performed for each read port, then address selection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the address decoding function into two parts: a first decoder that decodes a first portion of the address and a second decoder that decodes a second portion of the address. This segmentation allows the memory bitcell to use a single read port while still supporting multiple address spaces, as the combined decoding results determine which read port should be activated. This resolves the contradiction by maintaining data access capability through intelligent address segmentation rather than physically implementing multiple read ports.
Solution Approach 2:
Instead of performing full address decoding for each read port independently, the patent applies partial decoding by dividing the address into portions and using separate decoders for each portion. The first decoder handles the first portion and the second decoder handles the second portion, and their combined results are used to select the appropriate read port. This partial decoding approach reduces the complexity of each individual decoder while maintaining the ability to accurately select among multiple address spaces.
Data Source
AI summary
A hardware arrangement for a memory bitcell, including a primary decoder for decoding a common memory address portion among a plurality of memory addresses, and a plurality of secondary decoders each for decoding an uncommon memory address portion of each of the plurality of memory addresses. The memory bitcell is configured to receive the decoded common memory address portion and output data from a memory entry corresponding to the decoded common memory address portion, and includes a single read port for outputting the data. The hardware arrangement includes a modified sense amplifier (SA) configured to receive the data output on the single read port, and directly receive the plurality of decoded uncommon memory address portions. The plurality of decoded uncommon memory address portions is used to determine whether to enable the modified SA. Data output from the memory bitcell is forwarded when the modified SA is enabled.