Dynamically Allocable Non-Volatile Memory Regions
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Solution Overview
Problem
Flash memory devices have limitations in individual erasure and modification at the bit or byte level, restricting their application in complex operations due to block-level erasure constraints and low resolution.
Innovation Solution
A non-volatile memory device with individually programmable and erasable memory cells, allowing dynamic subdivision into subspaces for flexible operation, enabling independent programming and erasure of each cell and supporting advanced operations like copying without affecting entire blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If block-level erasure is used in flash memory, then erasure operation is simplified and implemented at reasonable cost, but memory resolution is insufficient for individual cell modification
Solution Approach 1:
The memory device is segmented into multiple independently erasable sub-blocks within each physical block. The block is divided into first sub-blocks and second sub-blocks, where each sub-block can be independently erased while others remain intact. This segmentation enables fine-grained control at the sub-block level, allowing individual cell or small group erasure without affecting the entire block, thus resolving the contradiction between ease of manufacture and memory resolution.
2Manufacturing precision
If individual memory cell erasure is enabled, then memory resolution is improved for precise modification, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent introduces a logical organization dimension overlaying the physical block structure. Memory cells are organized into dynamic regions and sub-blocks that can be independently managed through logical addressing and control signals. This additional logical dimension allows individual cell or selective group erasure without requiring complete reorganization of the physical block structure, thereby achieving high resolution while controlling complexity through logical rather than physical restructuring.
3Adaptability or versatility
If dynamic region allocation is implemented, then operational flexibility is enhanced for complex operations, but control mechanism complexity increases
Solution Approach 1:
The patent implements dynamic region allocation where the boundaries and sizes of memory regions can be adjusted during operation based on application requirements. Regions can be dynamically created, merged, split, or reconfigured without physical restructuring of the memory array. This dynamic logical organization provides high operational flexibility for complex operations while avoiding the complexity of physical reconfiguration mechanisms.
Data Source
AI summary
An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.