PRAM Word Line Driver Layout for Core Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase change random access memory (PRAM) devices have a large core area due to the need for isolation between PMOS and NMOS transistors in the word line driving circuit, which increases the device size and reduces the number of cells that can be simultaneously selected and increases current consumption.
Innovation Solution
The implementation of a word line driver layout that includes precharge and discharge devices alternately located between memory cell blocks, allowing for shared word lines and reducing the size of the isolation area between transistors, thereby minimizing the core area of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation area is provided between PMOS and NMOS transistors in the word line driving circuit, then transistor operation stability is improved, but device core area increases
Solution Approach 1:
The word line driving circuit is segmented into separate precharge device and discharge device sections, with memory cell blocks positioned between them. This segmentation allows the isolation area to be distributed and shared across multiple functional units rather than concentrated in one location, reducing the overall core area while maintaining transistor operation stability.
Solution Approach 2:
The isolation area between PMOS and NMOS transistors serves multiple functions: it provides electrical isolation for transistor stability and simultaneously acts as a shared structural element for the word line driving circuit. This multi-functionality reduces the total area required while maintaining the necessary isolation for reliable operation.
2Reliability
If larger core area is used, then transistor isolation is improved, but the number of simultaneously selectable cells decreases
Solution Approach 1:
The memory device is divided into multiple memory cell blocks that can be independently selected and operated. Each block has its own precharge and discharge devices, allowing simultaneous selection and operation of multiple blocks without requiring a single large isolation area, thus improving both transistor isolation and the number of simultaneously selectable cells.
3Reliability
If larger core area is used, then transistor isolation is improved, but current consumption increases
Solution Approach 1:
The word line driving circuit is segmented into separate precharge and discharge devices with memory cell blocks positioned between them. This segmentation reduces the total isolation area required, thereby reducing capacitance and current consumption while maintaining transistor isolation through the distributed isolation structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a reduction in the core area of the phase change memory device, allowing for simultaneous data writing or reading in multiple memory cells and reducing current consumption, while maintaining the stability and speed of phase-change characteristics.
Implementation Method 1
a precharge device for precharging the word line and a discharge device for discharging the word line
Implementation Method 2
the phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state
Implementation Method 3
the phase-change material of the PRAM is reset to an amorphous state by heating the material in excess of its melting point temperature
Data Source
AI summary
A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.