Configurable Die with Generic PHYs for LPDDR3 and LPDDR4 Support
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Solution Overview
Problem
Existing SoC dies are costly to retrofit for supporting different memory architectures like LPDDR3 and LPDDR4, limiting flexibility in price-sensitive markets where vendors need to balance price and performance.
Innovation Solution
A configurable die with generic PHYs and flexible signal logic that can communicate CA and DQ signals, allowing it to support both LPDDR3 and LPDDR4 memory types without additional routing layers, enabling simple and cost-effective interconnections in a PoP configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an SoC die is optimized for LPDDR4 packaging, then memory transfer rate and power efficiency are improved, but the cost of retrofitting for LPDDR3 increases significantly
Solution Approach 1:
The patent implements a universal die design where generic PHYs can be configured to support multiple memory types (LPDDR3 and LPDDR4) through software control. The same physical interface and routing infrastructure serve both memory standards, eliminating the need for separate optimized designs for each memory type and reducing retrofit costs.
Solution Approach 2:
The patent introduces dynamic configurability where the die can adapt its behavior based on the connected memory type. A logic element receives input signals identifying the memory type and dynamically configures the generic PHYs accordingly, allowing the system to optimize performance for the specific memory standard being used while maintaining hardware compatibility.
2Adaptability or versatility
If a configurable die with generic PHYs is used to support multiple memory types, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of separate LPDDR3-specific and LPDDR4-specific PHYs into a single generic PHY design. By combining these functions and using a logic element to dynamically configure the generic PHY based on memory type detection, the patent reduces the number of separate hardware components needed while maintaining support for multiple memory standards.
3Adaptability or versatility
If separate routing layers are added to support different memory architectures, then compatibility is improved, but packaging complexity increases
Solution Approach 1:
The patent implements universal routing infrastructure that can accommodate both LPDDR3 and LPDDR4 memory architectures without requiring separate dedicated routing layers. The same physical routing paths are used for both memory types, with the difference being in how the generic PHYs are configured to interpret and utilize these shared routing resources.
Data Source
AI summary
A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.